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FDC87W21 power i/o controller with fast infrared support features 5 volt operation plug & play 1.0a compliant supports eight irqs, four dma channels, 480 relocatable addresses floppy disk controller (fdc) - compatible with ibm pc/at disk drive systems - variable write precompensation with track selectable capability - dma enable logic - supports floppy disk drives and tape drives - detects all over-run and under-run conditions - data rate and drive control registers - built-in address mark detection circuit to simplify the read electronics - ibm pc system address decoder - 24 mhz crystal input (48 mhz when for 2 mbps fast tape drive) - fdd anti-virus functions with software write protect and fdd write enable signal (write data signal was forced to be inactive) - supports up to four 3.5-inch or 5.25- inch floppy disk drives - completely compatible with industry standard 82077/ 765a - supports 360k/720k/1.2m/1.44m/2.88m format; 250 kbps, 300 kbps, 500 kbps, 1 mbps, 2 mbps data transfer rate - supports perpendicular recording format - supports 3-mode fdd and win95 driver - 16-byte data fifos serial ports - two high-speed 16550 compatible uarts with 16-byte send/receive fifos - midi compatible - fully programmable serial-interface characteristics: - 5, 6, 7 or 8-bit characters - even, odd or no parity bit generation/detection - 1, 1.5 or 2 stop bits generation - internal diagnostic capabilities: - loop-back controls for communications link fault isolation - break, parity, overrun, framing error simulation - programmable baud generator allows division of 1.8461 mhz and 24 mhz by 1 to (2 16 -1) - maximum baud rate is up to 911.6 (8 times of 115.2 kbps) for 1.8461 mhz and 1.5 mbps for 24 mhz infrared - supports irda version 1.0 sir protocol with maximum baud rate up to 115.2 kbps - supports sharp ask-ir protocol with maximum baud rate up to 57600 bps - supports irda version 1.1 mir (1.152 mbps) and fir (4 mbps) protocol - two dma channel for transmitter and receiver - 32-byte fifo is supported in the tx/rx terminal
2 - 8-byte status fifo is supported to store received frame status (such as overrun, crc error, etc.) - supports auto-config sir and fir parallel port - compatible with ibm parallel port - supports parallel port with bi- directional lines - supports enhanced parallel port (epp) - compatible with ieee 1284 specification - supports extended capabilities port (ecp) - compatible with ieee 1284 specification - extension fdd mode supports disk drive b; and extension 2fdd mode supports disk drives a and b through parallel port - extension adapter mode supports pocket devices through parallel port - joystick mode supports joystick through parallel port isa host interface ide - supports up to two embedded hard disk drives (ide at bus) programmable configuration settings immediate or automatic power-down mode for power management all hardware power-on settings have internal pull-up or pull-down resistors as default value 100 pin qfp package general description the FDC87W21 is an enhanced version of the fdc87w22 --- which integrates the disk drive adapter, serial port (uart), irda 1.0 sir, parallel port, ide interface, configurable plug- and-play registers for the whole chip --- adding powerful features: irda 1.1 (mir for 1.152 mbps or fir for 4 mbps), tv remote ir. in addition to the function enhancement, FDC87W21 is pin-to- pin compatible to fdc87w22. the disk drive adapter functions of the FDC87W21 include a floppy disk drive controller compatible with the industry standard 82077/765 data separator, write pre- compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, interrupt and dma logic. the wide range of functions integrated into the FDC87W21 greatly reduces the number of components required for interfacing with floppy disk drives. the FDC87W21 supports up to 4 three-mode floppy disk drives (fdd) of formats 360k, 720k, 1.2m, 1.44m, or 2.88m, and data transfer rates of 250 kbps, 300 kbps, 500 kbps, 1 mbps, and 2 mbps. the FDC87W21 provides two high-speed serial communication ports (uarts), one of which supports serial infrared communication. each uart includes a 16-byte send/receive fifo , a programmable baud rate generator, complete modem control capability, and a processor interrupt system. one of uart supports infrared (ir) includes 32-byte fifo, serial ir (115, 200 bps), mir (1.152 mbps or 0.576 mbps), fir (4 mbps), and tv remote ir (supported nec, rc- 5, extended rc-5, and recs-80 protocols). the FDC87W21 supports one pc-compatible printer port (spp), bi-directional printer port (bpp), and also enhanced parallel port (epp) and extended capabilities port (ecp). through the printer port interface pins, also available are: extension fdd mode and extension 2fdd mode allowing one or two external floppy disk drives to be attached. especially in the application of notebook computer, this feature is very useful. the extension adapter mode of the FDC87W21 also allows pocket devices to be installed through the printer interface pins in notebook computer applications according to a protocol set by smsc, but with upgraded performance. the joystick mode allows a joystick to be connected to a parallel port with a signal switching cable.
3 the FDC87W21 supports two embedded hard disk drive (ide at bus) interfaces and a game port with decoded read/write output. the configuration registers support mode selection, function enable/disable, and power down function selection. moreover, the configurable pnp registers are compatible with the plug-and-play feature in windows 95 ? , which makes system resource allocation more efficient than ever. standard microsystems is a registered trademark and smsc is a trademark of standard microsystems corporation. other product and company names are trademarks or registered trademarks of their respective holders.
4 table of contents features ................................ ................................ ................................ ................................ ....... 1 general description ................................ ................................ ................................ ................ 2 pin configuration ................................ ................................ ................................ ...................... 6 pin description ................................ ................................ ................................ ........................ 7 h ost i nterface ................................ ................................ ................................ .............................. 7 fdc functional description ................................ ................................ ................................ . 17 FDC87W21 fdc ................................ ................................ ................................ .......................... 17 register descriptions ................................ ................................ ................................ ........ 31 ide ................................ ................................ ................................ ................................ .................. 42 ide d ecode d escription ................................ ................................ ................................ .............. 42 uart port ................................ ................................ ................................ ................................ ... 43 u niversal a synchronous r eceiver /t ransmitter (uart a, uart b) ................................ ............ 43 r egister a ddress ................................ ................................ ................................ ........................ 43 ir p ort ................................ ................................ ................................ ................................ ........ 54 parallel port ................................ ................................ ................................ ........................... 83 printer interface logic ................................ ................................ ................................ ..... 83 enhanced parallel port (epp) ................................ ................................ .......................... 85 extended capabilities parallel (ecp) port ................................ ................................ .. 89 e xtension fdd m ode (extfdd) ................................ ................................ ................................ .. 98 e xtension 2fdd m ode (ext2fdd) ................................ ................................ .............................. 98 e xtension a dapter m ode (extadp) (p atent pending ) ................................ ................................ . 98 j oystick m ode (p atent pending ) ................................ ................................ ................................ ... 99 game port decoder ................................ ................................ ................................ ............... 100 plug and play configuration ................................ ................................ ............................ 100 extended function registers ................................ ................................ ............................ 100 e xtended f unctions e nable r egisters (efer s ) ................................ ................................ .......... 101 e xtended f unction i ndex r egisters (efir s ), e xtended f unction d ata r egisters (efdr s ) ........ 101 b it m ap c onfiguration r egisters ................................ ................................ ............................... 137 specifications ................................ ................................ ................................ .......................... 139 a bsolute m aximum r atings ................................ ................................ ................................ .......... 139 dc characteristics ................................ ................................ ................................ ............. 139 ac c haracteristics ................................ ................................ ................................ .................... 141 timing waveforms ................................ ................................ ................................ .................. 147 fdc ................................ ................................ ................................ ................................ ............ 147 uart/p arallel ................................ ................................ ................................ ........................... 149 m odem c ontrol t iming ................................ ................................ ................................ ................ 150 p arallel p ort ................................ ................................ ................................ ............................. 151 p arallel p ort t iming ................................ ................................ ................................ .................. 151 epp d ata or a ddress r ead c ycle (epp v ersion 1.9) ................................ ................................ .. 152 epp d ata or a ddress w rite c ycle (epp v ersion 1.9) ................................ ................................ 153 epp d ata or a ddress r ead c ycle (epp v ersion 1.7) ................................ ................................ .. 154
5 epp d ata or a ddress w rite c ycle (epp v ersion 1.7) ................................ ................................ 155 p arallel p ort fifo t iming ................................ ................................ ................................ ......... 155 ecp p arallel p ort f orward t iming ................................ ................................ ........................... 156 ecp p arallel p ort r everse t iming ................................ ................................ ............................. 156 e xtension a dapter m ode c ommand c ycle ................................ ................................ ................... 157 e xtension a dapter m ode i nterrupt c ycle ................................ ................................ .................. 157 e xtension a dapter m ode dma c ycle ................................ ................................ .......................... 158 application circuits ................................ ................................ ................................ .............. 158 p arallel p ort e xtension fdd ................................ ................................ ................................ .... 158 p arallel p ort e xtension fdd ................................ ................................ ................................ .... 159 p arallel p ort e xtension 2fdd ................................ ................................ ................................ .. 160 p arallel p ort j oystick m ode ................................ ................................ ................................ ..... 161 f our fdd m ode ................................ ................................ ................................ .......................... 161 package dimensions ................................ ................................ ................................ .............. 162 80 arkay drive hauppauge, ny 11788 (516) 435-6000 fax (516) 273-3123
6 pin configuration 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 nindex nstep ndsa ndsb nwe nwd nrwc nhead ndir gnd nidben irq_b nirqin ncs0 ncs1 irq_a tc ndack_b irq_f drq_b nmob nmoa ntrak0 nwp ndskchg a10 nrdata d7 d6 d5 d4 d3 d2 d1 d0 gnd niow nior aen a9 a8 a7 a6 a5 vdd a4 a3 a2 a1 a0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nrib ndcdb ndsrb nctsb ndtrb nrtsb irq_c soutb sinb ngmrd gnd ngmwr souta irq_d nrtsa ndtra nctsa ndsra ndcda nria 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nreside ncs npdcin drq_c iochrdy mr xtal1 xtal2 pd0 pd1 pd2 pd3 pd4 pd5 vdd pd6 pd7 ndack_c nstb nafd ninit nslin irq_e busy gnd nack pe slct nerr sina FDC87W21
pin description (note: refer to the dc characteristics section for details.) i/o8tc ttl level output pin with 8 ma source-sink capability; cmos level input voltage i/o12t ttl level bi-directional pin with 12 ma source-sink capability i/o24t ttl level bi-directional pin with 24 ma source-sink capability out8t ttl level output pin with 8 ma source-sink capability out12t ttl level output pin with 12 ma source-sink capability od12 open-d rain output pin with 12 ma sink capability od24 open-drain output pin with 24 ma sink capability int ttl level input pin ints ttl level schmitt-triggered input pin inc cmos level input pin incs cmos level schmitt-triggered input pin host interface symbol pin i/o function host interface d0 - d7 66-73 i/o 24t system data bus bits 0-7 a0 - a9 51-55 57-61 in t system address bus bits 0-9 a10 75 in t in ecp mode, this pin is the a10 address input. iochrdy 5 od 24 in epp mode, this pin is the io channel ready output to extend the host read/write cycle. mr 6 in ts master reset. active high. mr is low during normal operations. ncs ndack_n irsl1 irsl2 2 in t in t out 12t out 12t active low chip select signal. dma acknowledge signal d. ir module mode select 1. ir module mode select 2. aen 62 in t system address bus enable nior 63 in ts cpu i/o read signal niow 64 in ts cpu i/o write signal drq_b 100 out 12t dma request signal b ndack_b 98 in ts dma acknowledge signal b drq_c 4 out 12t dma request signal c ndack_c 18 in ts dma acknowledge signal c tc 97 in ts terminal count. when active, this pin indicates termination of a dma transfer. irqin drq_d irsl2 irrxh/ irsl0 93 in t out 12t out 12t i/o 12t interrupt request input. dma request signal d. ir module mode selection 2. when input , act as a function of high speed ir receiving terminal. when output selected, act as a ir module mode selection 0. irq_a gio1 96 out 12t i/o 12t when cr16 bit 4 (goiqsel) = 0: interrupt request signal a; when cr16 bit 4 (goiqsel) = 1: general purpose i/o port 1. irq_b gio0 92 out 12t i/o 12t when cr16 bit 4 (goiqsel) = 0: interrupt request signal b; when cr16 bit 4 (goiqsel) = 1: general purpose i/o port 0. irq_c 44 out 12t interrupt request signal c
8 symbol pin i/o function irq_d 37 out 12t interrupt request signal d irq_e 23 out 12t interrupt request signal e irq_f 99 out 12t interrupt request signal f xtal1 7 clk in xtal oscillator input xtal2 8 clk out xtal oscillator output serial port interface nctsa nctsb 34 47 in t in t clear to send is the modem control input. the function of these pins can be tested by reading bit 4 of the handshake status register. ndsra ndsrb 33 48 in t in t data set ready. an active low indicates the modem or data set is ready to establish a communication link and transfer data to the uart. ndcda ndcdb 32 49 in t in t data carrier detect. an active low indicates the modem or data set has detected a data carrier. nria nrib 31 50 in t in t ring indicator. an active low indicates that a ring signal is being received by the modem or data set. sina sinb/ irrx1 30 42 in t in t serial input. used to receive serial data from the communication link. souta pin2ipsel 38 o 8tc i 8tc uart a serial output. used to transmit serial data out to the communication link. during power-on reset, this pin is pulled up internally and is defined as pin2ipsel, which provides the power-on value for cr16 bit 1 (pin2ipsel). a 4.7 k is recommended when intends to pull down at power-on reset. soutb irtx1 pgmdrq 43 o 8tc o 8tc i 8tc uart b serial output. used to transmit serial data out to the communication link. during power-on reset, this pin is pulled down internally and is defined as pgmdrq, which provides the power-on value for cr16 bit 3 (gmdrq). a 4.7 k is recommended when intends to pull up at power-on reset. ndtra phefras 35 o 8tc i 8tc uart a data terminal ready. an active low informs the modem or data set that the controller is ready to communicate. during power-on reset, this pin is pulled down internally and is defined as phefras, which provides the power-on value for cr16 bit 0 (hefras). a 4.7 k is recommended when intends to pull up at power-on reset. ndtrb 46 o 8t uart b data terminal ready. an active low informs the modem or data set that controller is ready to communicate. nrtsa ppnpcvs 36 o 8tc i 8tc uart a request to send. an active low informs the modem or data set that the controller is ready to send data. during power-on reset, this pin is pulled up internally and is defined as ppnpcvs, which provides the power-on value for cr16 bit 2 (pnpcvs). a 4.7 k is recommended when intends to pull down at power-on reset.
9 symbol pin i/o function nrtsb pgoiqsel 45 o 8tc i 8tc uart b request to send. an active low informs the modem or data set that the controller is ready to send data. during power-on reset, this pin is pulled down internally and is defined as pgoiqsel, which provides the power-on value for cr16 bit 4 (goiqsel). a 4.7 k is recommended when intends to pull up at power-on reset. game port/power down interface if bit 3 of cr16 (gmdrq) is 1, bit 4 of cr3 (gmods0) determines whether the game port is in adapter mode or portable mode (default is adapter mode). if bit 3 of cr16 is 0, pin 39 and 41 are used for dma a operation. ngmrd 41 out 8t when cr16 bit 3 (gmdrq) = 1, adapter mode: game port read control signal. pfdcen out 8t portable mode: when parallel port is selected as extension fdd/extension 2fdd mode, this pin will be active. the active state is dependent on bit 7 of cra (pfdcact), and default is low active. ndack_a in t when cr16 bit 3 (gmdrq) = 0, dma acknowledge signal a. ngmwr 39 out 8t when cr16 bit 3 (gmdrq) = 1, adapter mode: game port write control signal. pexten out 8t portable mode: when a particular extended mode is selected for the parallel port, this pin will be active. the extended modes include extension adapter mode, epp mode, ecp mode, and ecp/epp mode, which are selected using bit 3 - bit 0 of cra. the active state is dependent on bit 6 of cra (pextact); the default is low active. drq_a out 8t when cr16 bit 3 (gmdrq) = 0: dma request signal a. pdcin 3 in t this input pin controls the chip power down. when this pin is active, the clock supply to the chip will be inhibited and the output pins will be tri-stated as defined in cr4 and cr6. the pdcin is pulled down internally. its active state is defined by bit 4 of cra (pdchact). default is high active. ndack_n in t dma acknowledge signal d. irsl1 out 12t ir module mode select 1. irrxh/ irsl0 i/o 12t when input pin, high speed ir received terminal. when as output pin, ir module mode select 0. input or output are definied in high speed ir register. multi-mode parallel port the following pins have eight functions, which are controlled by bits prtmod0, prtmod1, and prtmod2 of cr0 and cr9. (refer to the extended functions section).
10 symbol pin i/o function busy 24 in t od 12 in t od 12 - printer mode: busy an active high input indicates that the printer is not ready to receive data. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nmob2 this pin is for extension fdd b; the function of this pin is the same as that of the nmob pin. extension adapter mode: xirq this pin is an interrupt request generated by the extension adapter and is an active high input. extension 2fdd mode: nmob2 this pin is for extension fdd a and b; the function of this pin is the same as that of the nmob pin. joystick mode: nc pin. nack 26 in t od 12 in t od 12 - printer mode: nack an active low input on this pin indicates that the printer has received data and is ready to accept more data. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndsb2 this pin is for the extension fdd b; its functions are the same as those of the ndsb pin. extension adapter mode: xdrq dma request generated by the extension adapter. an active high input. extension 2fdd mode: ndsb2 this pin is for extension fdd a and b; this function of this pin is the same as that of the ndsb pin. joystick mode: nc pin. pe 27 in t od 12 out 12t od 12 - printer mode: pe an active high input on this pin indicates that the printer has detected the end of the paper. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nwd2 this pin is for extension fdd b; its function is the same as that of the nwd pin. extension adapter mode: xa0 this pin is system address a0 for the extension adapter extension 2fdd mode: nwd2 this pin is for extension fdd a and b; this function of this pin is the same as that of the nwd pin. joystick mode: nc pin.
11 symbol pin i/o function slct 28 in t od 12 out 12t od 12 - printer mode: slct an active high input on this pin indicates that the printer is selected. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: we2 this pin is for extension fdd b; its functions are the same as those of the nwe pin. extension adapter mode: xa1 this pin is system address a1 for the extension adapter. extension 2fdd mode: nwe2 this pin is for extension fdd a and b; this function of this pin is the same as that of the nwe pin. joystick mode: nc pin. nerr 29 in t od 12 out 12t od 12 - printer mode: nerr an active low input on this pin indicates that the printer has encountered an error condition. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nhead2 this pin is for extension fdd b; its function is the same as that of the nhead pin. extension adapter mode: xa2 this pin is system address a2 for the extension adapter. extension 2fdd mode: nhead2 this pin is for extension fdd a and b; its function is the same as that of the nhead pin. joystick mode: nc pin. nslin 22 od 12 od 12 out 12t od 12 out 12t printer mode: nslin output line for detection of printer selection. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nstep2 this pin is for extension fdd b; its function is the same as that of the nstep pin. extension adapter mode: xtc this pin is the dma terminal count for the extension adapter. the count is sent by tc directly. extension 2fdd mode: nstep2 this pin is for extension fdd a and b; its function is the same as that of the nstep pin. joystick mode: v dd for joystick.
12 symbol pin i/o function ninit 21 od 12 od 12 out 12t od 12 out 12t printer mode: ninit output line for the printer initialization. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndir this pin is for extension fdd b; its function is the same as that of the ndir pin. extension adapter mode: nxdack this pin is the dma acknowledge output for the extension adapter; the output is sent directly from npdackx. extension 2fdd mode: ndir2 this pin is for extension fdd a and b; its function is the same as that of the ndir pin. joystick mode: v dd for joystick. nafd 20 od 12 od 12 out 12t od 12 out 12t printer mode: nafd an active low output from this pin causes the printer to auto feed a line after a line is printed. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nrwc2 this pin is for extension fdd b; its function is the same as that of the nrwc pin. extension adapter mode: nxrd this pin is the i/o read command for the extension adapter. when the extension adapter base address is written to the extension adapter address register, nxrd and nxwr go low simultaneously so that the command register on the extension adapter can latch the same base address. extension 2fdd mode: nrwc2 this pin is for extension fdd a and b; its function is the same as that of the nrwc pin. joystick mode: v dd for joystick. nstb 19 od 12 - out 12t - out 12t printer mode: nstb an active low output is used to latch the parallel data into the printer. this pin is pulled high internally. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension adapter mode: nxwr this pin is the i/o write command for the extension adapter. when the extension adapter base address is written to the extension adapter address register, nxrd and nxwr go low simultaneously so that the command register on the extension adapter can latch the same base address. extension 2fdd mode: this pin is a tri-state output. joystick mode: v dd for joystick.
13 symbol pin i/o function pd0 9 i/o 24t in t i/o 24t in t i/o 24t printer mode: pd0 parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nindex2 this pin is for extension fdd b; the function of this pin is the same as that of the nindex pin. this pin is pulled high internally. extension adapter mode: xd0 this pin is system data bus d0 for the extension adapter. extension 2fdd mode: nindex2 this pin is for extension fdd a and b; this function of this pin is the same as nindex pin. this pin is pulled high internally. joystick mode: jp0 this pin is the paddle 0 input for joystick. pd1 10 i/o 24t in t i/o 24t in t i/o 24t printer mode: pd1 parallel port data bus bit 1. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ntrak02 this pin is for extension fdd b; the function of this pin is the same as that of the ntrak0 pin. this pin is pulled high internally. extension adapter mode: xd1 this pin is system data bus d1 for the extension adapter. extension. 2fdd mode: ntrak02 this pin is for extension fdd a and b; this function of this pin is the same as ntrak0 pin. this pin is pulled high internally. joystick mode: jp1 this pin is the paddle 1 input for joystick. pd2 11 i/o 24t in t i/o 24t in t - printer mode: pd2 parallel port data bus bit 2. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nwp2 this pin is for extension fdd b; the function of this pin is the same as that of the nwp pin. this pin is pulled high internally. extension adapter mode: xd2 this pin is system data bus d2 for the extension adapter. extension. 2fdd mode: nwp2 this pin is for extension fdd a and b; this function of this pin is the same as that of the nwp pin. this pin is pulled high internally. joystick mode: nc pin
14 symbol pin i/o function pd3 12 i/o 24t in t i/o 24t in t - printer mode: pd3 parallel port data bus bit 3. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: nrdata2 motor on b for extension fdd b; the function of this pin is the same as that of the nrdata pin. this pin is pulled high internally. extension adapter mode: xd3 this pin is system data bus d3 for the extension adapter. extension 2fdd mode: nrdata2 this pin is for extension fdd a and b; function of this pin is the same as that of the nrdata pin. this pin is pulled high internally. joystick mode: nc pin pd4 13 i/o 24t in t i/o 24t in t in t printer mode: pd4 parallel port data bus bit 4. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: ndskchg2 drive select b for extension fdd b; the function of this pin is the same as that of ndskchg pin. this pin is pulled high internally. extension adapter mode: xd4 this pin is system data bus d4 for the extension adapter. extension 2fdd mode: ndskchg2 this pin is for extension fdd a and b; this function of this pin is the same as that of the ndskchg pin. this pin is pulled high internally. joystick mode: jb0 this pin is the button 0 input for the joystick. pd5 14 i/o 24t - i/o 24t - in t printer mode: pd5 parallel port data bus bit 5. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension adapter mode: xd5 this pin is system data bus d5 for the extension adapter. extension 2fdd mode: this pin is a tri-state output. joystick mode: jb1 this pin is the button 1 input for the joystick. pd6 16 i/o 24t - i/o 24t od 24 - printer mode: pd6 parallel port data bus bit 6. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension adapter mode: xd6 this pin is system data bus d6 for the extension adapter. extension. 2fdd mode: nmoa2 this pin is for extension fdd a; its function is the same as that of the nmoa pin. joystick mode: nc pin
15 symbol pin i/o function pd7 17 i/o 24t - i/o 24t od 24 - printer mode: pd7 parallel port data bus bit 7. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: this pin is a tri-state output. extension adapter mode: xd7 this pin is system data bus d7 for the extension adapter. extension 2fdd mode: ndsa2 this pin is for extension fdd a; its function is the same as that of the ndsa pin. joystick mode: nc pin ide and fdc interface nreside irq_g drq_d irsl2 1 out 12t out 12t out 12t out 12t when cr16 bit 1 (iride) = 0: active low reset signal for ide; when cr16 bit 1 (iride) = 1: interrupt request signal g. dma request signal. ir module mode select 2. nidben irq_h irsl2 ndack_n irrxh/ irsl0 91 out 12t out 12t out 12t in t i/o 12t when cr16 bit 1 (iride) = 0: active low enable signal for ide; when cr16 bit 1 (iride) = 1: interrupt request signal h. ir module mode selection 2. dma acknowledge signal d. when input selected, act as high speed ir receiving terminal. when output selected, act as ir module mode selection 0. ncs1 irtx2 95 out 12t out 12t when cr16 bit 1 (iride) = 0: this pin is used to select the ide controller. ncs1 decodes the hdc addresses specified in cr22. when cr16 bit 1 (iride) = 1: function as a infrared transmission data line. ncs0 irrx2 94 out 12t in t when cr16 bit 1 (iride) = 0: this pin is used to select the ide controller. ncs0 decodes hdc addresses specified in cr21. when cr16 bit 1 (iride) = 1: function as a infrared receiving line. nwe 85 od 24 write enable. an open drain output. ndir 89 od 24 direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion nhead 88 od 24 head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 nrwc 87 od 24 reduced write current. this signal can be used on two-speed disk drives to select the transfer rate. an open drain output. logic 0 = 250 kbps logic 1 = 500 kbps when bit 5 of cr9 (en3mode) is set to high, the three-mode fdd function is enabled, and the pin will have a different definition. refer to the en3mode bit in cr9. nwd 86 od 24 write data. this logic low open drain writes precompensation serial data to the selected fdd. an open drain output. nstep 82 od 24 step output pulses. this active low open drain output produces a pulse to move the head to another track.
16 symbol pin i/o function nindex 81 in cs this schmitt input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. this input pin is pulled up internally by an approximately 1k ohm resistor. the resistor can be disabled by bit 4 of cr6 (fipurdwn). ntrak0 78 in cs track 0. this schmitt input from the disk drive is active low when the head is positioned over the outermost track. this input pin is pulled up internally by an approximately 1k ohm resistor. the resistor can be disabled by bit 4 of cr6 (fipurdwn). nwp 77 in cs write protected. this active low schmitt input from the disk drive indicates that the diskette is write-protected. this input pin is pulled up internally by an approximately 1k ohm resistor. the resistor can be disabled by bit 4 of cr6 (fipurdwn). nrdata 74 in cs the read data input signal from the fdd. this input pin is pulled up internally by an approximately 1k ohm resistor. the resistor can be disabled by bit 4 of cr6 (fipurdwn). ndskchg 76 in cs diskette change. this signal is active low at power on and whenever the diskette is removed. this input pin is pulled up internally by an approximately 1k ohm resistor. the resistor can be disabled by bit 4 of cr6 (fipurdwn). nmoa 79 od 24 motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. nmob 80 od 24 motor b on. when set to 0, this pin enables disk drive 1. this is an open drain output. ndsa 83 od 24 drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. ndsb 84 od 24 drive select b. when set to 0, this pin enables disk drive b. this is an open drain output. v dd 15, 56 +5 volt power supply for the digital circuitry gnd 25, 40, 65, 90 ground
17 fdc functional description FDC87W21 fdc the floppy disk controller of the FDC87W21 integrates all of the logic required for floppy disk control. the fdc implements a pc/at or ps/2 solution. all programmable options default to compatible values. the fifo provides better system performance in multi-master systems. the digital data separator supports up to data rate 1 mbps. (2 mbps for fast tape drive with 48 mhz crystal in.) the fdc includes the following blocks: at interface, precompensation, data rate selection, digital data separator, fifo, and fdc core. at interface the interface consists of the standard asynchronous signals: nrd, nwr, a0-a3, irq, dma control, and a data bus. the address lines select between the configuration registers, the fifo and control/status registers. this interface can be switched between pc/at, model 30, or ps/2 normal modes. the ps/2 register sets are a superset of the registers found in a pc/at. fifo (data) the fifo is 16 bytes in size and has programmable threshold values. all command parameter information and disk data transfers go through the fifo. data transfers are governed by the rqm and dio bits in the main status register. the fifo defaults to disabled mode after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command. the advantage of the fifo is that it allows the system a larger dma latency without causing disk errors. the following tables give several examples of the delays with a fifo. the data are based upon the following formula: threshold (1/data rate) *8 - 1.5 m s = delay fifo threshold maximum delay to servicing at 500 kbps data rate 1 byte 1 16 m s - 1.5 m s = 14.5 m s 2 byte 2 16 m s - 1.5 m s = 30.5 m s 8 byte 8 16 m s - 1.5 m s = 6.5 m s 15 byte 15 16 m s - 1.5 m s = 238.5 m s fifo threshold maximum delay to servicing at 1 mbps data rate 1 byte 1 8 m s - 1.5 m s = 6.5 m s 2 byte 2 8 m s - 1.5 m s = 14.5 m s 8 byte 8 8 m s - 1.5 m s = 62.5 m s 15 byte 15 8 m s - 1.5 m s = 118.5 m s
18 at the start of a command the fifo is always disabled and command parameters must be sent based upon the rqm and dio bit settings in the main status register. when the fdc enters the command execution phase, it clears the fifo of any data to ensure that invalid data are not transferred. an overrun and underrun will terminate the current command and the data transfer. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered. dma transfers are enabled with the specify command and are initiated by the fdc by activating the drq pin during a data transfer command. the fifo is enabled directly by asserting ndack and addresses need not be valid. note that if the dma controller is programmed to function in verify mode a pseudo read is performed by the fdc based only on ndack. this mode is only available when the fdc has been configured into byte mode (fifo disabled) and is programmed to do a read. with the fifo enabled the above operation is performed by using the new verify command. no dma operation is needed. data separator the function of the data separator is to lock onto the incoming serial read data. when a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. the synchronized clock, called the data window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. serial to parallel conversion logic separates the read data into clock and data bytes. the digital data separator (dds) has three parts: control logic, error adjustment, and speed tracking. the dds circuit cycles once every 12 clock cycles ideally. any data pulse input will be synchronized and then adjusted by immediate error adjustment. the control logic will generate rdd and rwd for every pulse input. during any cycle where no data pulse is present, the dds cycles are based on speed. a digital integrator is used to keep track of the speed changes in the input data stream. write precompensation the write precompensation logic is used to minimize bit shifts in the rddata stream from the disk drive. shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive. the fdc monitors the bit stream that is being sent to the drive. the data patterns that require precompensation are well known. depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. perpendicular recording mode the fdc is also capable of interfacing directly to perpendicular recording floppy drives. perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. this scheme packs more data bits into the same area. fdcs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive. a single command puts the fdc into perpendicular mode. all other commands operate as they normally do. the perpendicular mode requires a 1 mbps data rate for the fdc. at this data rate the fifo eases the host interface bottleneck due to the speed of data transfer to or from the disk.
19 tape drive the FDC87W21 supports standard tape drives (1 mbps, 500 kbps, 250 kbps) and new fast tape drive (2 mbps). when working at 2 mbps, you need to change the crystal to 48 mhz. fdc core the FDC87W21 fdc is capable of performing twenty commands. each command is initiated by a multi-byte transfer from the microprocessor. the result can also be a multi- byte transfer back to the microprocessor. each command consists of three phases: command, execution, and result. command the microprocessor issues all required information to the controller to perform a specific operation. execution the controller performs the specified operation. result after the operation is completed, status information and other housekeeping information is provided to the microprocessor.
20 fdc commands command symbol descriptions: c: cylinder number 0 - 256 d: data pattern dir: step direction dir = 0, step out dir = 1, step in ds0: disk drive select 0 ds1: disk drive select 1 dtl: data length ec: enable count eot: end of track efifo: enable fifo eis: enable implied seek eot: end of track fifothr: fifo threshold gap: gap length selection gpl: gap length h: head number hds: head number select hlt: head load time hut: head unload time lock: lock efifo, fifothr, ptrtrk bits prevent affected by software reset mfm: mfm or fm mode mt: multitrack n: the number of data bytes written in a sector ncn: new cylinder number nd: non-dma mode ow: overwritten pcn: present cylinder number poll: polling disable pretrk: precompensation start track number r: record rcn: relative cylinder number r/w: read/write sc: sector/per cylinder sk: skip deleted data address mark srt: step rate time st0: status register 0 st1: status register 1 st2: status register 2 st3: status register 3 wg: write gate alters timing of we
21 fdc instruction sets (1) read data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
22 (2) read deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
23 (3) read a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system; fdd reads contents of all cylinders from index hole to eot result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
24 (4) read id phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ disk status after the command has been completed (5) verify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- -------------------- dtl/sc ------------------- execution no data transfer takes place result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
25 (6) version phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command codes result w 1 0 0 1 0 0 0 0 enhanced controller (7) write data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w -------------------- eot ----------------------- -------------------- gpl ----------------------- w -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
26 (8) write deleted data phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- c ------------------------ ---------------------- h ------------------------ sector id information prior to command execution w w ---------------------- r ------------------------ ---------------------- n ------------------------ w w w -------------------- eot ----------------------- -------------------- gpl ----------------------- -------------------- dtl ----------------------- execution data transfer between the fdd and system result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ sector id information after command execution
27 (9) format a track phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w w ---------------------- n ------------------------ --------------------- sc ----------------------- bytes/sector sectors/cylinder w w --------------------- gpl --------------------- ---------------------- d ------------------------ gap 3 filler byte execution for each sector repeat: w w w w ---------------------- c ------------------------ ---------------------- h ------------------------ ---------------------- r ------------------------ ---------------------- n ------------------------ input sector parameters result r r r -------------------- st0 ----------------------- -------------------- st1 ----------------------- -------------------- st2 ----------------------- status information after command execution r r r r ---------------- undefined ------------------- ---------------- undefined ------------------- ---------------- undefined ------------------- ---------------- undefined -------------------
28 (10) recalibrate phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt (11) sense interrupt status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes result r r ---------------- st0 ------------------------- ---------------- pcn ------------------------- status information at the end of each seek operation (12) specify phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w w | ---------srt ----------- | --------- hut ---------- | |------------ hlt -----------------------------------| nd (13) seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------------------- ncn ----------------------- execution r head positioned over proper cylinder on diskette (14) configure phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w w 0 eis efifo poll | ------ fifothr ----| | --------------------pretrk ---------------------- | execution internal registers written
29 (15) relative seek phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w | -------------------- rcn ---------------------------- | (16) dumpreg phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 registers placed in fifo result r r r r r r r r r r -------------------- pcn-drive 0----------------- -------------------- pcn-drive 1 ---------------- -------------------- pcn-drive 2----------------- -------------------- pcn-drive 3 ---------------- -------srt ----------------- | --------- hut -------- ------------ hlt -------------------------------------| nd -------------------- sc/eot -------------------- lock 0 d3 d2 d1 d0 gap wg 0 eis efifo poll | --- fifothr ---- | --------------------pretrk --------------------- (17) perpendicular mode phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command code w ow 0 d3 d2 d1 d0 gap wg (18) lock phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command code result r 0 0 0 lock 0 0 0 0
30 (19) sense drive status phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command code w 0 0 0 0 0 hds ds1 ds0 result r ---------------- st3 ------------------------- status information about disk drive (20) invalid phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w ------------- invalid codes ----------------- invalid codes (no operation - fdc goes into standby state) result r -------------------- st0 ---------------------- st0 = 80h
31 register descriptions there are several status, data, and control registers in FDC87W21. these registers are defined below: address register offset read write base address + 0 base address + 1 base address + 2 base address + 3 sa register sb register td register do register td register base address + 4 ms register dr register base address + 5 dt (fifo) register dt (fifo) register base address + 7 di register cc register status register a (sa register) (read base address + 0) this register is used to monitor several disk interface pins in ps/2 and model 30 modes. in ps/2 mode, the bit definitions for this register are as follows: init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. ndrv2 (bit 6): 0 a second drive has been installed 1 a second drive has not been installed step (bit 5): this bit indicates the complement of nstep output. ntrak0 (bit 4): this bit indicates the value of ntrak0 input. head (bit 3): this bit indicates the complement of nhead output. 0 side 0 1 side 1 1 2 3 4 5 6 7 0 nw p nindex head ntrak0 step ndrv2 init pending dir
32 nindex (bit 2): this bit indicates the value of nindex output. nwp (bit 1): 0 disk is write-protected 1 disk is not write-protected dir (bit 0) this bit indicates the direction of head movement. 0 outward direction 1 inward direction in ps/2 model 30 mode, the bit definitions for this register are as follows: init pending (bit 7): this bit indicates the value of the floppy disk interrupt output. drq (bit 6): this bit indicates the value of drq output pin. step f/f (bit 5): this bit indicates the complement of latched nstep output. trak0 (bit 4): this bit indicates the complement of ntrak0 input. nhead (bit 3): this bit indicates the value of nhead output. 0 sid e 1 1 side 0 index (bit 2): this bit indicates the complement of nindex output. wp (bit 1): 0 disk is not write-protected 1 disk is write-protected 1 2 3 4 5 6 7 0 wp index nhead trak0 step f/f drq init pending ndir
33 ndir (bit 0) this bit indicates the direction of head movement. 0 inward direction 1 outward direction status register b (sb register) (read base address + 1) this register is used to monitor several disk interface pins in ps/2 and model 30 modes. in ps/2 mode, the bit definitions for this register are as follows: drive sel0 (bit 5): this bit indicates the status of do register bit 0 (drive select bit 0). wdata toggle (bit 4): this bit changes state at every rising edge of the nwd output pin. rdata toggle (bit 3): this bit changes state at every rising edge of the nrdata output pin. we (bit 2): this bit indicates the complement of the nwe output pin. mot en b (bit 1) this bit indicates the complement of the nmob output pin. mot en a (bit 0) this bit indicates the complement of the nmoa output pin. in ps/2 model 30 mode, the bit definitions for this register are as follows: 1 2 3 4 5 6 7 0 mot en a we rdata toggle wdata toggle drive sel0 mot en b 1 1
34 ndrv (bit 7): 0 a second drive has been installed 1 a second drive has not been installed ndsb (bit 6): this bit indicates the status of ndsb output pin. ndsa (bit 5): this bit indicates the status of ndsa output pin. wd f/f (bit 4): this bit indicates the complement of the latched nwd output pin at every rising edge of the nwd output pin. rdata f/f (bit 3): this bit indicates the complement of the latched nrdata output pin . we f/f (bit 2): this bit indicates the complement of latched nwe output pin. ndsd (bit 1): 0 drive d has been selected 1 drive d has not been selected ndsc (bit 0): 0 drive c has been selected 1 drive c has not been selected digital output register (do register) (write base address + 2) the digital output register is a write-only register controlling drive motors, drive selection, drq/irq enable, and fdc resetting. all the bits in this register are cleared by the mr pin. the bit definitions are as follows: 1 2 3 4 5 6 7 0 ndsc ndsd we f/f rdata f/f ndsa ndsb ndrv2 wd f/f
35 7 6 5 4 3 2 1-0 drive select: 00 select drive a 01 select drive b 10 select drive c 11 select drive d floppy disk controller reset active low resets fdc dma and int enable active high enable drq/irq motor enable a. motor a on when active high motor enable b. motor b on when active high motor enable c. motor c on when active high motor enable d. motor d on when active high tape drive register (td register) (read base address + 3) this register is used to assign a particular drive number to the tape drive support mode of the data separator. this register also holds the media id, drive type, and floppy boot drive information of the floppy disk drive. in normal floppy mode, this register includes only bit 0 and 1. the bit definitions are as follows: 1 2 3 4 5 6 7 0 tape sel 0 tape sel 1 x x x x x x if three mode fdd function is enabled (en3mode = 1 in cr9), the bit definitions are as follows: 1 2 3 4 5 6 7 0 floppy boot drive 0 floppy boot drive 1 drive type id0 drive type id1 media id0 media id1 tape sel 0 tape sel 1 media id1 media id0 (bit 7, 6): these two bits are read only. these two bits reflect the value of cr8 bit 3, 2. drive type id1 drive type id0 (bit 5, 4): these two bits reflect two of the bits of cr7. which two bits are reflected depends on the last drive selected in the do register. floppy boot drive 1, 0 (bit 3, 2): these two bits reflect the value of cr8 bit 1, 0. tape sel 1, tape sel 0 (bit 1, 0):
36 these two bits assign a logical drive number to the tape drive. drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive. tape sel 1 tape sel 0 drive selected 0 0 none 0 1 1 1 0 2 1 1 3 main status register (ms register) (read base address + 4) the main status register is used to control the flow of data between the microprocessor and the controller. the bit definitions for this register are as follows: data rate register (dr register) (write base address + 4) the data rate register is used to set the transfer rate and write precompensation. the data rate of the fdc is programmed by the cc register for pc-at and ps/2 model 30 and ps/2 mode, and not by the dr register. the real data rate is determined by the most recent write to either of the dr register or cc register. 1 2 3 4 5 6 7 0 drate0 drate1 precomp0 precomp1 precomp2 power down s/w reset 0 s/w reset (bit 7): this bit is the software reset bit. fdd 0 busy, (d0b = 1), fdd number 0 is in the seek mode. fdd 1 busy, (d1b = 1), fdd number 1 is in the seek mode. fdc busy, (cb). a read or write command is in the process when cb = high. non-dma mode, the fdc is in the non-dma mode, this bit is set only during the execution phase in non-dma mode. transition to low state indicates execution phase has ended. data input/output, (dio). if dio= high then transfer is from data register to the processor. if dio = low then transfer is from processor to data register. request for master (rqm). a high on this bit indicates data register is ready to send or receive data to or from the processor. 7 6 5 4 3 2 1 0 fdd 2 busy, (d2b = 1), fdd number 2 is in the seek mode. fdd 3 busy, (d3b = 1), fdd number 3 is in the seek mode.
37 power-down (bit 6): 0 fdc in normal mode 1 fdc in power-down mode precomp2 precomp1 precomp0 (bit 4, 3, 2): these three bits select the value of write precompensation. the following tables show the precompensation values for the combination of these bits. precom 2 1 0 precompensation delay 0 0 0 default delays 0 0 1 41.67 ns 0 1 0 83.34 ns 0 1 1 125.00 ns 1 0 0 166.67 ns 1 0 1 208.33 ns 1 1 0 250.00 ns 1 1 1 0.00 ns (disabled) data rate default precompensation delays 250 kbps 125 ns 300 kbps 125 ns 500 kbps 125 ns 1 mbps 41.67 ns drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc and reduced write current control. 00 500 kbps (mfm), 250 kbps (fm), nrwc = 1. 01 300 kbps (mfm), 150 kbps (fm), nrwc = 0. 10 250 kbps (mfm), 125 kbps (fm), nrwc = 0. 11 1 mbps (mfm), illegal (fm), nrwc = 1. fifo register (r/w base address + 5) the data register consists of four status registers in a stack with only one register presented to the data bus at a time. this register stores data, commands, and parameters and provides diskette-drive status information. data bytes are passed through the data register to program or obtain results after a command. in the FDC87W21, this register defaults to fifo disabled mode after reset. the fifo can change its value and enable its operation through the configure command.
38 status register 0 (st0) status register 1 (st1) 7-6 5 4 3 2 1-0 us1, us0 drive select: 00 drive a selected 01 drive b selected 10 drive c selected 11 drive d selected hd head address: 1 head selected 0 head selected nr not ready: 1 drive is not ready 0 drive is ready ec equipment check: 1 when a fault signal is received from the fdd or the track 0 signal fails to occur after 77 step pulses 0 no error se seek end: 1 seek end 0 seek error ic interrupt code: 00 normal termination of command 01 abnormal termination of command 10 invalid command issue 11 abnormal termination because the ready signal from fdd changed state during command execution missing address mark. 1 when the fdc cannot detect the data address mark or the data address mark has been deleted. nw (not writable). 1 if a write protect signal is detected from the diskette drive during execution of write data. nd (no data). 1 if specified sector cannot be found during execution of a read, write or verifly data. not used. this bit is always 0. or (over rum). 1 if the fdc is not serviced by the host system within a certain time interval during data transfer. de (data error) .1 when the fdc detects a crc error in either the id field or the data field. not used. this bit is always 0. en (end of track). 1 when the fdc tries to access a sector beyond the final sector of a cylinder. 0 1 2 3 4 5 6 7
39 status register 2 (st2) 1 2 3 4 5 6 7 0 bc (bad cylinder) md (missing address mark in data field). 1 if the fdc cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 no error 1 bad cylinder 0 no error sn (scan not satisfied) 1 during execution of the scan command 0 no error sh (scan equal hit) 1 during execution of the scan command, if the equal condition is satisfied 0 no error wc (wrong cylinder) 1 indicates wrong cylinder dd (data error in the data field) 1 if the fdc detects a crc error in the data field 0 no error cm (control mark) 1 during execution of the read data or scan command 0 no error not used. this bit is always 0 status register 3 (st3) 1 2 3 4 5 6 7 0 us0 unit select 0 us1 unit select 1 hd head address ts two-side to track 0 ry ready wp write protected ft fault digital input register (di register) (read base address + 7) the digital input register is an 8-bit read-only register used for diagnostic purposes. in a pc/xt or at only bit 7 is checked by the bios. when the register is read, bit 7 shows the complement of ndskchg, while other bits of the data bus remain in tri-state. bit definitions are as follows: x x x x x x x x 0 1 2 3 4 5 6 7 reserved for the hard disk controller during a read of this register, these bits are in tri-state dskchg
40 in the ps/2 mode, the bit definitions are as follows: dskchg (bit 7): this bit indicates the complement of the ndskchg input. bit 6-3: these bits are always a logic 1 during a read. drate1 drate0 (bit 2, 1): these two bits select the data rate of the fdc. refer to the dr register bits 1 and 0 for the settings corresponding to the individual data rates. nhigh dens (bit 0): 0 500 kbps or 1 mbps data rate (high density fdd) 1 250 kbps or 300 kbps data rate in the ps/2 model 30 mode, the bit definitions are as follows: dskchg (bit 7): this bit indicates the status of ndskchg input. bit 6-4: these bits are always a logic 1 during a read. dmaen (bit 3): this bit indicates the value of do register bit 3. noprec (bit 2): 1 2 3 4 5 6 7 0 nhigh dens drate0 drate1 dskchg 1 1 1 1 1 2 3 4 5 6 7 0 drate0 drate1 ndskchg noprec dmaen 0 0 0
41 this bit indicates the value of cc register noprec bit. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. configuration control register (cc register) (write base address + 7) this register is used to control the data rate. in the pc/at and ps/2 mode, the bit definitions are as follows: x x x x x x drate0 drate1 0 1 2 3 4 5 7 6 x: reserved bit 7-2: reserved. these bits should be set to 0. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc. in the ps/2 model 30 mode, the bit definitions are as follows: 1 2 3 4 5 6 7 0 drate0 drate1 noprec x x x x x x : reserved bit 7-3: reserved. these bits should be set to 0. noprec (bit 2): this bit indicates no precompensation. it has no function and can be set by software. drate1 drate0 (bit 1, 0): these two bits select the data rate of the fdc.
42 ide the ide interface is essentially the at bus ported to the hard disk drive. the hard disk controller resides on the ide hard disk drive. so the ide interface provides only chip select signals and at bus signals between the ide hard disk drive and isa slot. table 1 shows the ide registers and their isa addresses. table 1 i/o address registers offset read write ncs0 base address + 0 data register data register ncs0 base address + 1 error register write-precomp ncs0 base address + 2 sector count sector count ncs0 base address + 3 sector number sector number ncs0 base address + 4 cylinder low cylinder low ncs0 base address + 5 cylinder high cylinder high ncs0 base address + 6 sdh register sdh register ncs0 base address + 7 status register command register ncs0 base address + 6 alternate status fixed disk control ide decode description when the processor selects the addresses which match the ones specified in cr 21, the chip system enables ncs0 = low; otherwise, ncs0 = high. when the processor selects the address which matches the one specified in cr22, the chip system enables ncs1 = low; otherwise, ncs1 = high.
43 uart port universal asynchronous receiver/transmitter (uart a, uart b) the uarts are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. the serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. the uarts are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uarts also support the midi data rate. furthermore, the uarts also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. the uarts have a fifo mode to reduce the number of interrupts presented to the cpu. in each uart, there are 16-byte fifos for both receive and transmit mode. register address uart register bit map bit number register address base 0 1 2 3 8 bdlab = 0 r eceiver buffer r egister (read only) rbr rx data bit 0 rx data bit 1 rx data bit 2 rx data bit 3 8 bdlab = 0 t ransmitter b uffer r egister ( write only) tbr tx data bit 0 tx data bit 1 tx data bit 2 tx data bit 3 9 bdlab = 0 i nterrupt c ontrol r egister icr rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) usr interrupt enable (eusri) hsr interrupt enable (ehsri) a i nterrupt s tatus r egister ( read only ) isr "0" if interrupt pending interrupt status bit (0) interrupt status bit (1) interrupt status bit (2)** a u art fifo c ontrol r egister (write only) ufr fifo enable rcvr fifo reset xmit fifo reset dma mode select b u art c ontrol r egister ucr data length select bit 0 (dls0) data length select bit 1 (dls1) multiple stop bits enable (msbe) parity bit enable (pbe) c h andshake c ontrol r egister hcr data terminal ready (dtr) request to send (rts) loopback ri input irq enable d u art s tatus register usr rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) e h andshake s tatus r egister hsr cts toggling (tcts) dsr toggling (tdsr) ri falling edge (feri) dcd toggling (tdcd) f u ser d efined r egister udr bit 0 bit 1 bit 2 bit 3
44 8 bdlab = 1 b audrate d ivisor l atch l ow bll bit 0 bit 1 bit 2 bit 3 9 bdlab = 1 b audrate d ivisor l atch h igh bhl bit 8 bit 9 bit 10 bit 11 *: bit 0 is the least significant bit. the least significant bit is the first bit serially transmitted or received. **: these bits are always 0 in 16450 mode.
45 bit number register address base 4 5 6 7 8 bdlab = 0 r eceiver buffer r egister (read only) rbr rx data bit 4 rx data bit 5 rx data bit 6 rx data bit 7 8 bdlab = 0 t ransmitter b uffer r egister ( write only) tbr tx data bit 4 tx data bit 5 tx data bit 6 tx data bit 7 9 bdlab = 0 i nterrupt c ontrol r egister icr 0 0 0 0 a i nterrupt s tatus r egister ( read only ) isr 0 0 fifos enabled ** fifos enabled ** a u art fifo c ontrol r egister (write only) ufr reserved reversed (reserved ???) rx interrupt active level (lsb) rx interrupt active level (msb) b u art c ontrol r egister ucr even parity enable (epe) parity bit fixed enable pbfe) set silence enable (sse) baud rate divisor latch access bit (bdlab) c h andshake c ontrol r egister hcr internal loopback enable 0 0 0 d u art s tatus register usr silent byte detected (sbd) tbr empty (tbre) tsr empty (tsre) rx fifo error indication (rfei) ** e h andshake s tatus r egister hsr clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) f u ser d efined r egister udr bit 4 bit 5 bit 6 bit 7 8 bdlab = 1 b audrate d ivisor l atch l ow bll bit 4 bit 5 bit 6 bit 7 9 bdlab = 1 b audrate d ivisor l atch h igh bhl bit 12 bit 13 bit 14 bit 15 *: bit 0 is the least significant bit. the least significant bit is the first bit serially transmitted or received. **: these bits are always 0 in 16450 mode.
46 uart control register (ucr) (read/write) the uart control register controls and defines the protocol for asynchronous data communications , including data length, stop bit, parity, and baud rate selection. 1 2 3 4 5 6 7 0 data length select bit 0 (dls0) data length select bit 1(dls1) multiple stop bits enable (msbe) parity bit enable (pbe) even parity enable (epe) parity bit fixed enable (pbfe) set silence enable (sse) baudrate divisor latch access bit (bdlab) bit 7: bdlab. when this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format) from the divisor latches of the baud rate generator during a read or write operation. when this bit is reset, the receiver buffer register, the transmitter buffer register, or the interrupt control register can be accessed. bit 6: sse. a logical 1 forces the serial output (sout) to a silent state (a logical 0). only sout is affected by this bit; the transmitter is not affected. bit 5: pbfe. when pbe and pbfe of ucr are both set to a logical 1, (1) if epe is a logical 1, the parity bit is fixed as a logical 0 to transmit and check. (2) if epe is a logical 0, the parity bit is fixed as a logical 1 to transmit and check. bit 4: epe. this bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. when this bit is set, an even number of logic 1's are sent or checked. when the bit is reset, an odd number of logic 1's are sent or checked. bit 3: pbe. when this bit is set, the position between the last data bit and the stop bit of the sout will be stuffed with the parity bit at the transmitter. for the receiver, the parity bit in the same position as the transmitter will be detected. bit 2: msbe. this bit defines the number of stop bits in each serial character that is transmitted or received. (1) if msbe is set to a logical 0, one stop bit is sent and checked. (2) if msbe is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and checked. (3) if msbe is set to a logical 1, and data le ngth is 6, 7, or 8 bits, two stop bits are sent and checked. bits 0 and 1: dls0, dls1. these two bits define the number of data bits that are sent or checked in each serial character.
47 word length definition dls1 dls0 data length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits uart status register (usr) (read/write) this 8-bit register provides information about the status of the data transfer during communication. 1 2 3 4 5 6 7 0 rbr data ready (rdr) overrun error (oer) parity bit error (pber) no stop bit error (nser) silent byte detected (sbd) transmitter buffer register empty (tbre) transmitter shift register empty (tsre) rx fifo error indication (rfei) bit 7: rfei. in 16450 mode, this bit is always set to a logic 0. in 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the fifo. in 16550 mode, this bit is cleared by reading from the usr if there are no remaining errors left in the fifo. bit 6: tsre. in 16450 mode, when tbr and tsr are both empty, this bit will be set to a logical 1. in 16550 mode, if the transmit fifo and tsr are both empty, it will be set to a logical 1. other than these two cases, this bit will be reset to a logical 0. bit 5: tbre. in 16450 mode, when a data character is transferred from tbr to tsr, this bit will be set to a logical 1. if etrei of icr is a logical 1, an interrupt will be generated to notify the cpu to write the next data. in 16550 mode, this bit will be set to a logical 1 when the transmit fifo is empty. it will be reset to a logical 0 when the cpu writes data into tbr or fifo. bit 4: sbd. this bit is set to a logical 1 to indicate that received data are kept in silent state for a full word time, including start bit, data bits, parity bit, and stop bits. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 3: nser. this bit is set to a logical 1 to indicate that the received data have no stop bit. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0. bit 2: pber. this bit is set to a logical 1 to indicate that the parity bit of received data is wrong. in 16550 mode, it indicates the same condition for the data on top of the fifo. when the cpu reads usr, it will clear this bit to a logical 0.
48 bit 1: oer. this bit is set to a logical 1 to indicate received data have been overwritten by the next received data before they were read by the cpu. in 16550 mode, it indicates the same condition instead of fifo full. when the cpu reads usr, it will clear this bit to a logical 0. bit 0: rdr. this bit is set to a logical 1 to indicate received data are ready to be read by the cpu in the rbr or fifo. after no data are left in the rbr or fifo, the bit will be reset to a logical 0. handshake control register (hcr) (read/write) this register controls the pins of the uart used for handshaking peripherals such as modem, and controls the diagnostic mode of the uart. 0 0 0 0 1 2 3 4 5 6 7 data terminal ready (dtr) request to send (rts) loopback ri input irq enable internal loopback enable bit 4: when this bit is set to a logical 1, the uart enters diagnostic mode by an internal loopback, as follows: (1) sout is forced to a logical 1, and sin is isolated from the communication link instead of the tsr. (2) modem output pins are set to their inactive state. (3) modem input pins are isolated from the communication link and connect internally as dtr (bit 0 of hcr) ? ndsr, rts (bit 1 of hcr) ? ncts, loopback ri input (bit 2 of hcr) ? nri and irq enable (bit 3 of hcr) ? ndcd. aside from the above connections, the uart operates normally. this method allows the cpu to test the uart in a convenient way. bit 3: the uart interrupt output is enabled by setting this bit to a logic 1. in the diagnostic mode this bit is internally connected to the modem control input ndcd. bit 2: this bit is used only in the diagnostic mode. in the diagnostic mode this bit is internally connected to the modem control input nri. bit 1: this bit controls the nrts output. the value of this bit is inverted and output to nrts. bit 0: this bit controls the ndtr output. the value of this bit is inverted and output to ndtr. handshake status register (hsr) (read/write) this register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.
49 bit 7: this bit is the opposite of the ndcd input. this bit is equivalent to bit 3 of hcr in loopback mode. bit 6: this bit is the opposite of the nri input. this bit is equivalent to bit 2 of hcr in loopback mode. bit 5: this bit is the opposite of the ndsr input. this bit is equivalent to bit 0 of hcr in loopback mode. bit 4: this bit is the opposite of the ncts input. this bit is equivalent to bit 1 of hcr in loopback mode. bit 3: tdcd. this bit indicates that the ndcd pin has changed state after hsr was read by the cpu. bit 2: feri. this bit indicates that the nri pin has changed from low to high state after hsr was read by the cpu. bit 1: tdsr. this bit indicates that the ndsr pin has changed state after hsr was read by the cpu. bit 0: tcts. this bit indicates that the ncts pin has changed state after hsr was read by the cpu. uart fifo control register (ufr) (write only) this register is used to control the fifo functions of the uart. 1 2 3 4 5 6 7 0 fifo enable receiver fifo reset transmitter fifo reset dma mode select reserved reserved rx interrupt active level (lsb) rx interrupt active level (msb) bit 6, 7: these two bits are used to set the active level for the receiver fifo interrupt. for example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver fifo, the interrupt will be activated to notify the cpu to read the data from the fifo. 1 2 3 4 5 6 7 0 ri falling edge (feri) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) ncts toggling (tcts) ndsr toggling (tdsr) ndcd toggling (tdcd)
50 fifo trigger level bit 7 bit 6 rx fifo interrupt active level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 bit 4, 5: reserved bit 3: when this bit is programmed to logic 1, the dma mode will change from mode 0 to mode 1 if ufr bit 0 = 1. bit 2: setting this bit to a logical 1 resets the tx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. bit 1: setting this bit to a logical 1 resets the rx fifo counter logic to initial state. this bit will clear to a logical 0 by itself after being set to a logical 1. bit 0: this bit enables the 16550 (fifo) mode of the uart. this bit should be set to a logical 1 before other bits of ufr are programmed.
51 interrupt status register (isr) (read only) this register reflects the uart interrupt status, which is encoded by different interrupt sources into 3 bits. 1 2 3 4 5 6 7 0 0 if interrupt pending interrupt status bit 0 interrupt status bit 1 interrupt status bit 2 fifos enabled fifos enabled 0 0 bit 7, 6: these two bits are set to a logical 1 when ufr bit 0 = 1. bit 5, 4: these two bits are always logic 0. bit 3: in 16450 mode, this bit is 0. in 16550 mode, both bit 3 and 2 are set to a logical 1 when a time- out interrupt is pending. bit 2, 1: these two bits identify the priority level of the pending interrupt, as shown in the table below. bit 0: this bit is a logical 1 if there is no interrupt pending. if one of the interrupt sources has occurred, this bit will be set to a logical 0.
52 interrupt control function isr interrupt set and function bit 3 bit 2 bit 1 bit 0 interrupt priority interrupt type interrupt source clear interrupt 0 0 0 1 - - no interrupt pending - 0 1 1 0 first uart receive status 1. oer = 1 2. pber =1 3. nser = 1 4. sbd = 1 read usr 0 1 0 0 second rbr data ready 1. rbr data ready 2. fifo interrupt active level reached 1. read rbr 2. read rbr until fifo data under active level 1 1 0 0 second fifo data timeout data present in rx fifo for 4 characters period of time since last access of rx fifo. read rbr 0 0 1 0 third tbr empty tbr empty 1. write data into tbr 2. read isr (if priority is third) 0 0 0 0 fourth handshake status 1. tcts = 1 2. t dsr = 1 3. feri = 1 4. tdcd = 1 read hsr ** bit 3 of isr is enabled when bit 0 of ufr is logical 1. interrupt control register (icr) (read/write) this 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. the interrupt system can be totally disabled by resetting bits 0 through 3 of the interrupt control register (icr). a selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1. 0 0 0 1 2 3 4 5 6 7 0 0 rbr data ready interrupt enable (erdri) tbr empty interrupt enable (etbrei) uart receive status interrupt enable (eusri) handshake status interrupt enable (ehsri) bit 7-4: these four bits are always logic 0. bit 3: ehsri. setting this bit to a logical 1 enables the handshake status register interrupt. bit 2: eusri. setting this bit to a logical 1 enables the uart status register interrupt. bit 1: etbrei. setting this bit to a logical 1 enables the tbr empty interrupt.
53 bit 0: erdri. setting this bit to a logical 1 enables the rbr data ready interrupt. programmable baud generator (bll/bhl) (read/write) two 8-bit registers, bll and bhl, compose a programmable baud generator that uses 24 mhz to generate a 1.8461 mhz frequency and divides it by a divisor from 1 to 2 16 -1. the output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. the table below illustrates the use of the baud generator with a frequency of 1.8461 mhz. in high-speed uart mode (refer to cr0c bit7 and cr0c bit6), the programmable baud generator directly uses 24 mhz and the same divisor as the normal speed divisor. in high-speed mode, the data transmission rate can be as high as 1.5 mbps. user-defined register (udr) (read/write) this is a temporary register that can be accessed and defined by the user. baud rate table baud rate using 24 mhz to generate 1.8461 mhz desired baud rate decimal divisor used to generate 16x clock percent error difference between desired and actual 50 2304 ** 75 1536 ** 110 1047 0.18% 134.5 857 0.099% 150 768 ** 300 384 ** 600 192 ** 1200 96 ** 1800 64 ** 2000 58 0.53% 2400 48 ** 3600 32 ** 4800 24 ** 7200 16 ** 9600 12 ** 19200 6 ** 38400 3 ** 57600 2 ** 115200 1 ** 1.5m 1* 0% * only use in high speed mode (refer cr0c bit7 and cr0c bit6). ** the percentage error for all baud rates, except where indicated otherwise, is 0.16%.
54 ir port the FDC87W21 includes two serial ports: uart a and uart b. the second serial port, uart b, also has built in the infrared (ir) functions which include irda 1.0 sir, irda 1.1 mir (1.152 mbps), irda fir (4 mbps), sharp ask-ir, and remote control (that supports nec, rc-5, advanced rc-5, and recs-80 protocol). advanced uart b register description when bank select enable bit (enbnksel in cr2c.bit3) is set, uart b will be switched to advanced uart b, and eight register sets can be accessed. these register sets control enhanced uart b, ir function switching such as sir, mir, or fir. also a superior traditional uart b function can be use such as 32-byte transmitter/receiver fifo, non-encoding irq identify status register, and automatic flow control. the mir/fir and remote control registers are also defined in these register sets. the structure of the register sets is shown as follows. set 0 reg 7 reg 6 reg 5 reg 4 bdl/ssr reg 2 reg 1 reg 0 set 1 set 3 set 4 set 5 set 6 set 7 set 2 all in one reg to select ssr *set 0, 1 are legacy/advanced uart registers *set 2~7 are advanced uart registers
55 all sets' registers have a common register which is sets select register (ssr) in order to switch to any set when config this register. the summary description of these sets is shown in the following. set uart ir mode sets description 0 o o legacy/advanced uart control and status registers. 1 o o legacy baud rate divisor register. 2 o advanced uart control and status registers. 3 o version id and mapped control registers. 4 o transmitter/receiver/timer counter registers and ir control registers. 5 o flow control and ir control and frame status fifo registers. 6 o ir physical layer control registers 7 o remote control and ir front-end module selection registers. set0-legacy/advanced uart control and status registers address offset register name register description 0 rbr/tbr receiver/transmitter buffer registers 1 icr interrupt control register 2 isr/ufr interrupt status or uart fifo control register 3 ucr/ssr uart control or sets select register 4 hcr handshake control register 5 usr uart status register 6 hsr handshake status register 7 udr/escr user defined register set0.reg0 - receiver/transmitter buffer registers (rbr/tbr) (read/write) receiver buffer register is read only and transmitter buffer register is write only. these registers are described same as legacy uart. in the legacy uart, this port only supports pio mode. in the advanced uart, if setup to mir/fir/remote ir, this port will support dma handshake function. two dma channel can be used, that is one tx dma channel and another rx dma channel. therefore, single dma channel is also supported when set the bit of d_chsw (dma channel swap, in set2.reg2.bit3) and the tx/rx dma channel is swapped. note that two dma channels are defined in config register cr2a which select dma channel or disable dma channel. if enable rx dma channel and disable tx dma channel, then the single dma channel will be selected. set0.reg1 - interrupt control register (icr) mode b7 b6 b5 b4 b3 b2 b1 b0 uart 0 0 0 0 ehsri eusri etbrei erdri advanced uart etmri efsfi etxthi edmai ehsri eusri/ txuri etbrei erbri
56 where uart is used to legacy uart, and the functions for these bits are defined in the previous uart, nevertheless, the traditional sir or ask-ir based on the legacy uart also have same definitions. the advanced uart functions included advanced sir/ask-ir, mir, fir, or remote ir are described as follows. bit 7: etmri - enable timer interrupt write to 1, enable timer interrupt. bit 6: mir, fir mode: efsfi - enable frame status fifo interrupt write to 1 , enable frame status fifo interrupt. advanced sir/ask-ir, remote ir: not used. bit 5: advanced sir/ask-ir, mir, fir, remote ir: etxthi - enable transmitter threshold interrupt write to 1, enable transmitter threshold interrupt. bit 4: mir, fir, remote ir: edmai - enable dma interrupt. write to 1, enable dma interrupt. bit 3: advanced uart/sir/ask-ir, mir, fir, remote ir: ehsri - enable hsr (handshake status register) interrupt write to 1 , enable handshake status register interrupt. note that the bit irhssl (infrared handshake select) should be set to 1, then this bit ehsri is effective. bit 2: advanced sir/ask-ir: eusri - enable usr (uart status register) interrupt write to 1 , enable uart status register interrupt. mir, fir, remote controller: ehsri/etxuri - enable usr interrupt or enable transmitter underrun interrupt write to 1, enable usr interrupt or enable transmitter underrun interrupt. bit 1: etbrei - enable tbr (transmitter buffer register) empty interrupt write to 1 , enable transmitter buffer register empty interrupt. bit 0: erbri - enable rbr (receiver buffer register) interrupt write to 1 , enable receiver buffer register interrupt.
57 set0.reg2 - interrupt status register/uart fifo control register (isr/ufr) (1) interrupt status register: (read only) mode b7 b6 b5 b4 b3 b2 b1 b0 legacy uart fifo enable fifo enable 0 0 iid2 iid1 iid0 ip advanced uart tmr_i fsf_i txth_i dma_i hs_i usr_i/ fend_i txemp_i rxth_i reset value 0 0 1 0 0 0 1 0 legacy uart : same as previous register defined. advanced uart: bit 7: tmr_i - timer interrupt set to 1 when timer count to 0. this bit will be affected by (1) the timer registers are defined in set4.reg0 and set4.reg1, (2) en_ tmr(enable timer, in set4.reg2.bit0) should be set to 1, (3) entmr_i (enable timer interrupt, in set0.reg1.bit7) should be set to 1. bit 6: mir, fir modes: fsf_i - frame status fifo interrupt set to 1 when frame status fifo is equal or larger than the threshold level or frame status fifo time-out occurs. clear to 0 when frame status fifo is below the threshold level. advanced uart/sir/ask-ir, remote ir modes: not used. bit 5: txth_i - transmitter threshold interrupt set to 1 if the tbr (transmitter buffer register) fifo is below the threshold level. clear to 0 if the tbr (transmitter buffer register) fifo is below the threshold level. bit 4: mir, fir, remote ir modes: dma_i - dma interrupt set to 1 if the dma controller 8237a sends a tc (terminal count) to i/o device which that may be a transmitter tc or a receiver tc. clear to 0 when this register is read. bit 3: hs_i - handshake status interrupt set to 1 when the handshake status register has a toggle. clear to 0 when handshake status register (hsr) is read. note that in all ir modes included sir, ask-ir, mir, fir, and remote control ir are defaulted to inactive except set ir handshake status enable (irhs_en) to 1. bit 2: advanced uart/sir/ask-ir modes: usr_i - uart status interrupt set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the uart status register (usr ) sets to 1. clear to 0 when usr is read. mir, fir modes: fend_i - frame end interrupt
58 set to 1 when (1) a frame have a grace end to be detected where the frame signal is defined in the physical layer of irda version 1.1 (2) abort signal or illegal signal has been detected during receiving valid data. clear to 0 when this register is read. remote controller mode: not used. bit 1: txemp_i - transmitter empty set to 1 when transmitter (or, say, fifo + transmitter) is empty. clear to 0 when this register is read. bit 0: rxth_i - receiver threshold interrupt set to 1 when (1) the receiver buffer register (rbr) is equal or larger than the threshold level, (2) rbr occurs time-out if the receiver buffer register has valid data and below the threshold level. clear to 0 when rbr is less than threshold level from reading rbr. (2) uart fifo control register (ufr): mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 legacy uart rxftl1 (msb) rxftl0 (lsb) 0 0 0 txf_rst rxf_rst en_fifo advanced uart rxftl1 (msb) rxftl0 (lsb) txftl1 (msb) txftl0 (lsb) 0 txf_rst rxf_rst en_fifo reset value 0 0 0 0 0 0 0 0 legacy uart : the definition of this register is same as legacy uart mode. advanced uart: bit 7, 6: rxftl1, 0 - receiver fifo threshold level definition is same as legacy uart, that is to determine the rxth_i to become 1 when the receiver fifo threshold level is equal or larger than the defined value shown as follow. rxftl1, 0 (bit 7, 6) rx fifo threshold level (fifo size: 16-byte) rx fifo threshold level (fifo size: 32-byte) 00 1 1 01 4 4 10 8 16 11 14 26 note that the fifo size is referred to set2.reg4.
59 bit 5, 4: txftl1, 0 - transmitter fifo threshold level to determine the txth_i (transmitter threshold level interrupt) is set to 1 when the transmitter threshold level is less than the programmed value shown as follows. txftl1, 0 (bit 5, 4) tx fifo threshold level (fifo size: 16-byte ) tx fifo threshold level (fifo size: 32-byte ) 00 1 1 01 3 7 10 9 17 11 13 25 bit 3 ~0 same legacy uart mode set0.reg3 - uart control register/set select register (ucr/ssr): these two registers are shared same address. in any set, set select register (ssr) can be programmed to desired set, but uart control register can be programmed only in set 0 and set 1, that is, in other sets will not affect when program this register. the mapping of entry set and programming value is shown as follows. ssr bits selected 7 6 5 4 3 2 1 0 hex value set 0 x x x x x x x x set 0 1 any value but not used in set 2~7 x set1 1 1 1 0 0 0 0 0 0xe0 set 2 1 1 1 0 0 1 0 0 0xe4 set 3 1 1 1 0 1 0 0 0 0xe8 set 4 1 1 1 1 1 1 0 0 0xec set 5 1 1 1 1 0 0 0 0 0xf0 set 6 1 1 1 1 0 1 0 0 0xf4 set 7 uart control register : defined legacy uart. set0.reg4 - handshake control register (hcr) mode b7 b6 b5 b4 b3 b2 b1 b0 legacy uart 0 0 0 xloop en_irq lp_ri rts dtr advanced uart ad_md2 ad_md1 ad_md0 sir_pls tx_wt en_dma rts dtr reset value 0 0 0 0 0 0 0 0 legacy uart register: these registers are defined same as previous description. advanced uart register: bit 7~5 advanced uart/sir/ask-ir, mir, fir, remote controller modes: ad_md2~0 - advanced uart/infrared mode select.
60 these registers are active when advanced uart select (adv_sl, in set2.reg2.bit0) is set to 1. operational mode selection is defined as follows. when the backward operation occurs, these registers will be reset to 0 and backward legacy uart mode. ad_md2~0 (bit 7, 6, 5) selected mode 000 advanced uart 001 low speed mir (0.576 mbps) 010 advanced ask-ir 011 advanced sir 100 high speed mir (1.152 mbps) 101 fir (4 mbps) 110 consumer ir 111 reserved bit 4: mir, fir modes: sir_pls - send infrared pulse write to 1 then automatic send a 2 m s infrared pulse after physical frame end. in order to talk to sir that the high speed infrared is still in process when sends this pulse. this bit will be automatically cleared by hardware. other modes: not used. bit 3: mir, fir modes: tx_wt - transmission waiting if this bit sets to 1, the transmitter will wait for tx fifo reaching to threshold level or transmitter time-out which avoid short data bytes to want to transmit, then begins to transmit data from tx fifo. that is in order to avoid underrun. other modes: not used. bit 2: mir, fir modes: en_dma - enable dma enable dma function to trans mission or receiving. before using this, the dma channel should be select. if set rx dma channel and disable tx dma channel then the single dma channel is used. in the single channel system, the bit of d_chsw (dma channel swap, in set 2.reg2.bit3) will determine rx dma channel or tx dma channel. other modes: not used. bit 1, 0: rts, dtr functional definitions are same as legacy uart mode.
61 set0.reg5 - uart status register (usr) mode b7 b6 b5 b4 b3 b2 b1 b0 legacy uart rfei tsre tbre sbd nser pber oer rdr advanced uart lb_infr tsre tbre mx_lex phy_err crc_err oer rdr reset value 0 1 1 0 0 0 0 0 legacy uart register: these registers are defined same as previous description. advanced uart register: bit 7: mir, fir modes: lb_infr - last byte in frame end set to 1 when a last byte of a frame is in the fifo bottom. this bit indicates that separate one frame from another frame when rx fifo has more than one frame. bit 6, 5: same as legacy uart description. bit 4: mir, fir modes: mx_lex - maximu m frame length exceed set to 1 when frame length from the receiver has exceeded the programmed frame length which is in set4.reg6 and reg5.if this bit is set to 1, the receiver will not receive any data to rx fifo. bit 3: mir, fir modes: phy_err - phys ical layer error set to 1 when an illegal data symbol is received. where the illegal data symbol is defined in physical layer of irda version 1.1. when this bit is set to 1, the decoder of receiver will be aborted and a frame end signal is set to 1. bit 2: mir, fir modes: crc_err - crc error set to 1 when an attached crc is error. bit 1, 0: oer - overrun error, rdr - rbr data ready definitions are same as legacy uart. set0.reg6 - handshake status register (hsr) mode b7 b6 b5 b4 b3 b2 b1 b0 legacy uart dcd ri dsr cts tdcd feri tdsr tcts advanced uart dcd ri dsr cts tdcd feri tdsr tcts reset value 0 0 0 0 0 0 0 0 legacy/advanced uart register: these registers are defined same as previous description.
62 set0.reg7 - user defined register (udr/audr) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 legacy uart bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart flc_act undrn rx_bsy/ rx_ip lst_fe/ rx_pd s_fend 0 lb_sf rx_to reset value 0 0 0 0 0 0 0 0 legacy uart register: these registers are defined same as previous description. advanced uart register: bit 7 mir, fir modes: flc_act - flow control active set to 1 when the flow control occurs. clear to 0 when this register is read. note that this will be affected by set5.reg2 which control the sir mode switches to mir/fir mode or mir/fir mode operated in dma function switches to sir mode. bit 6 mir, fir modes: undrn - underrun set to 1 when transmitter is empty and not set s_fend (in this register bit 3) operated in pio mode or not tc (terminal count) operated in dma mode. clear to 0 when write to 1. bit 5 mir, fir modes: rx_bsy - receiver busy set to 1 when receiver is busy or active in process. remote ir mode: rx_ip - receiver in process set to 1 when receiver is i n process. bit 4: mir, fir modes: lst_fe - lost frame end set to 1 when a frame end in a entire frame is lost. clear to 0 when read this register. remote ir modes: rx_pd - receiver pulse detected set to 1 when one or more than one remote pul ses are detected. clear to 0 when read this register. bit 3 mir, fir modes: s_fend - set a frame end write to 1 when want to terminal the frame, that is, the procedure of pio command is an entire frame = write frame data (first) + write s_fend (last) this bit should be set to 1, if use in pio mode, to avoid transmitter underrun. note that this bit s_fend is set to 1 that is equivalent to tc (terminal count) in dma mode. this bit should be set to 0 in dma mode. bit 2: reserved.
63 bit 1: mir, fir modes: lb_sf - last byte stay in fifo set to 1 that indicates one or more than one frame end still stay in receiver fifo. bit 0: mir, fir, remote ir modes: rx_to - receiver fifo or frame status fifo time-out set to 1 when receiver fifo or frame status fifo occurs time-out set1 - legacy baud rate divisor register address offset register name register description 0 bll baud rate divisor latch (low byte) 1 bhl baud rate divisor latch (high byte) 2 isr/ufr interrupt status or uart fifo control register 3 ucr/ssr uart control or sets select register 4 hcr handshake control register 5 usr uart status register 6 hsr handshake status register 7 udr/escr user defined register set1.reg0~1 - baud rate divisor latch (bll/bhl) the two registers of bll and bhl are baud rate divisor latch in the legacy uart/sir/ask-ir mode. read/write these registers, if set in advanced uart mode, will occur backward operation, that is, will go to legacy uart mode and clear some register values shown table as follows. set & register advanced mode dis_back=x legacy mode dis_back=0 set 0.reg 4 bit 7~5 - set 2.reg 2 bit 0, 5, 7 bit 5, 7 set 4.reg 3 bit 2, 3 - note that dis_back=1 (disable backward operation) in legacy uart/sir/ask-ir mode will not affect any register which that can operate legacy sir/ask-ir. set1.reg 2~7 this register is defined as same as set 0 registers.
64 set2 - interrupt status or uart fifo control register (isr/ufr) these registers are only used in advanced modes. address offset register name register description 0 abll advanced baud rate divisor latch (low byte) 1 abhl advanced baud rate divisor latch (high byte) 2 adcr1 advanced uart control register 1 3 ssr sets select register 4 adcr2 advanced uart control register 2 5 reserved - 6 txfdth transmitter fifo depth 7 rxfdth receiver fifo depth reg0, 1 - advanced baud rate divisor latch (abll/abhl) the two registers are same as the legacy uart baud rate divisor latch in set 1. reg0~1. when use advanced uart/sir/ask-ir mode operation, should program these registers to set baud rate. that is to avoid to backward operation occurred. reg2 - advanced uart control register 1 (adcr1) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart br_out - en_lout aloop d_chsw dmathl dma_f adv_sl reset value 0 0 0 0 0 0 0 0 bit 7: br_out - baud rate clock output write to 1, then the programmed baud rate clock will output to dtr pin. this bit is only test baud rate divisor. bit 6: reserved, write 0. bit 5: en_lout - enable loopback output write to 1 , enable output transmitter data to irtx pin during doing loopback operation. setting this bit can check output data with internal data. bit 4: aloop - all mode loopback write to 1 , then enable loopback in all modes. bit 3: d_chsw - dma tx/rx channel swap if use signal dma channel in mir/fir mode, then the dma channel can be swapped. d_chsw - dma channel selected 0 receiver (default) 1 transmitter write to 1, then enable output data during the aloop=1. bit 2: dmathl - dma threshold level set dma threshold level as shown in the table below.
65 tx fifo threshold rx fifo threshold dmathl 16-byte 32-byte (16/32-byte) 0 13 13 4 1 23 7 10 bit 1: dma_f - dma fairness dma_f function description 0 dma reque st (dreq) is forced inactive after 10.5us 1 no effect dma request. bit 0: adv_sl - advanced mode select write to 1, then advanced mode is selected. reg3 - sets select register (ssr) read this register that returns e0 16 . write it to select other register set. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr ssr7 ssr6 ssr5 ssr4 ssr3 ssr2 srr1 srr0 default value 1 1 1 0 0 0 0 0 reg4 - advanced uart control register 2 (adcr2) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart dis_ back - pr_div1 pr_div0 rx_fsz1 rx_fsz0 tx_fsz1 txfsz0 reset value 0 0 0 0 0 0 0 0 bit 7: dis_back - disable backward operation write to 1, read or write bll or bhl (baud rate divisor latch register, in set1.reg0~1) will is disable backward legacy uart mode. when use legacy sir/ask-ir mode, this bit should be set to 1 to avoid backward operation. bit 6: reserved, write 0. bit 5, 4: pr_div1~0 - pre-divisor 1~0. these bits select pre-divisor for external input clock 24m hz. the clock through the pre- divisor then input to baud rate divisor of uart. pr_div1~0 pre-divisor max. baud rate 00 13.0 115.2 kbps 01 1.625 921.6 kbps 10 6.5 230.4 kbps 11 1 1.5 mbps bit 3, 2: rx_fsz1~0 - receiver fifo size 1~0 these bits setup receiver fifo size w hen fifo is enable.
66 rx_fsz1~0 rx fifo size 00 16-byte 01 32-byte 1x reserved bit 1, 0: tx_fsz1~0 - transmitter fifo size 1~0 these bits setup transmitter fifo size when fifo is enable. tx_fsz1~0 tx fifo size 00 16-byte 01 32-byte 1x reserved reg6 - transmitter fifo depth (txfdth) (read only) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart 0 0 txfd5 txfd4 txfd3 txfd2 txfd1 txfd1 reset value 0 0 0 0 0 0 0 0 bit 7~6: reserved, read 0. bit 5~0: read these bits will return th e current transmitter fifo depth, that is, how many bytes are there in the transmitter fifo. reg7 - receiver fifo depth (rxfdth) (read only) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart 0 0 rxfd5 rxfd4 rxfd3 rxfd2 rxfd1 rxfd1 reset value 0 0 0 0 0 0 0 0 bit 7~6: reserved, read 0. bit 5~0: read these bits will return the current receiver fifo depth, that is, how many bytes are there in the receiver fifo. set3 - version id and mapped control registers address offset register name register description 0 auid advanced uart id 1 mp_ucr mapped uart control register 2 mp_ufr mapped uart fifo control register 3 ssr sets select register 4 reversed - 5 reserved - 6 reserved - 7 reserved -
67 reg0 - advanced uart id (auid) this register is read only. indicate that advanced uart version id. read it and return 1x 16 . reg1 - mapped uart control register (mp_ucr) read only. read this register that returns uart control register value of set 0. reg2 - mapped uart fifo control register (mp_ufr) read only. read this register that returns uart fifo control register (ufr) value of set 0. reg3 - sets select register (ssr) read this register that returns e4 16 . write it to select other register set. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr ssr7 ssr6 ssr5 ssr4 ssr3 ssr2 srr1 srr0 default value 1 1 1 0 0 1 0 0 set4 - tx/rx/timer counter registers and ir control registers. address offset register name register description 0 tmrl timer value low byte 1 tmrh timer value high byte 2 ir_msl infrared mode select 3 ssr sets select register 4 tfrll transmitter frame length low byte 5 tfrlh transmitter frame length high byte 6 rfrll receiver frame length low byte 7 rfrlh receiver frame length high byte set4.reg0, 1 - timer value register (tmrl/tmrh) this is a 12-bit timer which resolution is 1 ms, that is, the programmed maximum time is 2 12 -1 ms. the timer is a down-counter. the timer start down count when the bit en_tmr (enable timer) of set4.reg2. is set to 1. when the timer down count to zero and en_tmr=1, the tmr_i is set to 1. when the counter down count to zero, a new initial value will be re-loaded into timer counter. set4.reg2 - infrared mode select (ir_msl) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 advanced uart - - - - ir_msl1 ir_msl0 tmr_tst en_tmr reset value 0 0 0 0 0 0 0 0 bit 7~4: reserved, write to 0.
68 bit 3, 2: ir_msl1, 0 - infrared mode select select legacy uart or sir or ask-ir mode. note that using legacy sir/ask-ir should set dis_back=1 to avoid backward when program baud rate. below is shown mode selected . note that to avoid legacy backward operation, the bit of dis_back (disable backward, in set2.reg4. bit7) should be set to 1 when legacy ask-ir mode or legacy sir mode is selected. ir_msl1, 0 operation mode selected 00 legacy uart 01 reserved 10 legacy ask-ir 11 legacy sir bit 1: tmr_tst - timer test write to 1, then reading the tmrl/tmrh will return the programmed values of tmrl/tmrh, that is, does not return down count counter value. this bit is for test timer register. bit 0: en_tmr - enable timer write to 1, enable the timer. set4.reg3 - set select register (ssr) read this register returns e8 16 . write this register to select other set. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr ssr7 ssr6 ssr5 ssr4 ssr3 ssr2 srr1 srr0 default value 1 1 1 1 1 0 0 0 set4.reg4, 5 - transmitter frame length (tfrll/tfrlh) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tfrll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value 0 0 0 0 0 0 0 0 tfrlh - - - bit 12 bit 11 bit 10 bit 9 bit 8 reset value - - - 0 0 0 0 0 these are 13-bit registers. write these registers , then the transmitter frame length of a package will be programmed. these registers are only used in apm=1 (automatic package mode, set5.reg4.bit5). when apm=1, the physical layer will split data stream to a programmed frame length if the transmitted data is larger than the programmed frame length. when read these registers, they will return the number of bytes which is not transmitted from a frame length programmed.
69 set4.reg6, 7 - receiver frame length (rfrll/rfrlh) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rfrll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value 0 0 0 0 0 0 0 0 rfrlh - - - bit 12 bit 11 bit 10 bit 9 bit 8 reset value - - - 0 0 0 0 0 these are 13-bit registers and combined a 13-bit up counter. program these registers, then the receiver frame length will be limited to the programmed frame length. if the received frame length is larger than the programmed receiver frame length, the bit of mx_lex (maximum length exceed) will be set to 1. simultaneously, the receiver will not receive any data to rx fifo until the next start flag in the next frame, which is defined in the physical layer irda 1.1, is reached and then the received data begin to write to rx fifo. read these registers will return the number of received data bytes from the receiver for a frame. set 5 - flow control and ir control and frame status fifo registers address offset register name register description 0 fcbll flow control baud rate divisor latch register (low byte) 1 fcbhl flow control baud rate divisor latch register (high byte) 2 fc_md flow control mode operation 3 ssr sets select register 4 ircfg1 infrared config register 5 fs_fo frame status fifo register 6 rfrlfl receiver frame length fifo low byte 7 rfrlfh receiver frame length fifo high byte set5.reg0, 1 - flow control baud rate divisor latch register (fcdll/ fcdhl) if occurs flow control from mir/fir mode change to sir mode, then the pre-programming baud rate of fcbll/fcbhl are loaded to advanced baud rate divisor latch (adbll/adbhl).
70 set5.reg2 - flow control mode operation (fc_md) these registers control flow control mode operation as shown in the table below. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fc_md fc_md2 fc_md1 fc_md0 - fc_dsw en_fd en_brfc en_fc reset value 0 0 0 0 0 0 0 0 bit 7~5 fc_md2 - flow control mode when occurs flow control state, these bits will b e loaded to ad_md2~0 of advanced hsr (handshake status register). these three bits defined are same as ad_md2~0. bit 4: reserved, write 0. bit 3: fc_dsw - flow control dma channel swap write to 1, when occurs flow control state, enable to swap dma chann el of both transmitter and receiver. fc_dsw next mode after flow control occurred 0 receiver channel 1 transmitter channel bit 2: en_fd - enable flow dma control write to 1 then enable to use dma channel when flow control is occurred. bit 1: en_br fc - enable baud rate flow control write to 1 then enable fc_bll/fc_bhl (flow control baud rate divider latch, in set5.reg1~0) to be loaded to advanced baud rate divisor latch (adbll/adbhl, in set2.reg1~0). bit 0: en_fc - enable flow control write to 1 then can use flow control function and bit 7~1 of this register can be activated. set5.reg3 - sets select register (ssr) write this register then change set of register. read this register will return ec 16 . reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr ssr7 ssr6 ssr5 ssr4 ssr3 ssr2 srr1 srr0 default value 1 1 1 0 1 1 0 0 set5.reg4 - infrared config register 1 (ircfg1) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ircfg1 - fsf_th fend_m aux_rx - - irhssl ir_full reset value 0 0 0 0 0 0 0 0
71 bit 7: reserved, write 0. bit 6: fsf_th - frame status fifo threshold set this bit to determine the frame status fifo threshold level and to generate the fsf_i. the threshold level values are defined as follows. fsf_th status fifo threshold level 0 2 1 4 bit 5: fend_md - frame end mode write to 1 then enable hardware automatically to split same length frame defined set4.reg4 and set4.reg5, i.e., tfrll/tfrlh. bit 4: aux_rx - auxiliary receiver pin write to 1, select irrx input pin. (refer to set7.reg7.bit5) bit 3~2: reserved, write 0. bit 1: irhssl - infrared handshake status select write to 0, then the hsr (handshake status register) is normal operation as same as uart. write to 1, then hsr will be disable, and read hsr will return 30 16 . bit 0: ir_full - infrared full duplex operation write to 0, then ir function is operated in half duplex. write to 1, then ir function is operated in full duplex. set5.reg5 - frame status fifo register (fs_fo) this register indicates the fifo bottom of frame status. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fs_fo fsfdr lst_fr - mx_lex phy_err crc_err rx_ov fsf_ov reset value 0 0 0 0 0 0 0 0 bit 7: fsfdr - frame status fifo data ready indicates that have a valid data in frame status fifo bottom. bit 6: lst_fr - lost frame set to 1 when one or more than one frame has been lost. bit 5: reserved. bit 4: mx_lex - maximum frame length exceed set to 1 when exceed programmed maximum frame length defined set4.reg6 and set4.reg7. this bit is frame status fifo bottom. to read this bit will return a valid value when fsfdr=1 (frame status fifo data ready).
72 bit 3: phy_err - physical error during receiving data, any physical layer error, defined irda 1.1, will be set to 1 in this bit. this bit is frame status fifo bottom. to read this bit will return a valid value when fsfdr=1 (frame status fifo data ready). bit 2: crc_err - crc error set to 1 when receive a bad crc in a frame. this crc belongs to physical layer defined in irda 1.1. this bit is frame status fifo bottom. to read this bit will return a valid value when fsfdr=1 (frame status fifo data ready). bit 1: rx_ov - received data overrun set to 1 when received data in fifo occur overrun. bit 0: fsf_ov - frame status fifo overrun set t o 1 when frame status fifo occur overrun. set5.reg6, 7 - receiver frame length fifo (rflfl/rflfh) or lost frame number (lst_nu) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rflfl/ lst_nu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value 0 0 0 0 0 0 0 0 rflfh - - - bit 12 bit 11 bit 10 bit 9 bit 8 reset value 0 0 0 0 0 0 0 0 receiver frame length fifo (rflfl/rflfh): these registers are 13-bit. read these registers will return received frame length. when read the register of rflfh will pop-up another frame status and frame length if fsfdr=1 (set5.reg4.bit7). lost frame number (lst_nu): when lst_fr=1 (set5.reg4. bit6), reg6 is replaced to lst_nu, that is 8-bit register and read rflfh will return 0. when read the register of rflfh will pop-up another frame status and frame length if fsfdr=1 (set5.reg4.bit7). set6 - ir physical layer control registers address offset register name register description 0 ir_cfg2 infrared config register 2 1 mir_pw mir (1.152mbps or 0.576mbps) pulse width 2 sir_pw sir pulse width 3 ssr sets select register 4 hir_fnu high speed infrared flag number 5 reserved - 6 reserved - 7 reserved -
73 set6.reg0 - infrared config register 2 (ir_cfg2) this register config ask-ir, mir, fir operation function. reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ir_cfg2 shmd_n shdm_n fir_crc mir_crc - inv_crc dis_crc - reset value 0 0 1 0 0 0 0 0 bit 7: shmd_n - ask-ir modulation disable shmd_n modulation mode 0 sout modulate 500khz square wave 1 re-rout sout bit 6: shdm_n - ask-ir demodulation disable shdm_n demodulation mode 0 demodulation 500khz 1 re-rout sin bit 5: fir_crc - fir (4m bps) crc type - note that the 16/32-bit crc are defined in irda 1.1 physical layer. fir_crc crc type 0 16-bit crc 1 32-bit crc bit 4: mir_crc - mir (1.152m/0.576m bps) crc type mir_crc crc type 0 16-bit crc 1 32-bit crc bit 2: inv_crc - inverting crc write to 1 then the crc is inverted output in physical layer. bit 1: dis_crc - disable crc write to 1 then the transmitter does not transmit crc in physical layer. bit 0: reserved, write 1. set6.reg1 - mir (1.152 mbps/0.576 mbps) pulse width reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mir_pw - - - m_pw4 m_pw3 m_pw2 m_pw1 m_pw0 reset value 0 0 0 0 1 0 1 0 this 5-bit register is set mir output pulse width.
74 m_pw4~0 mir pulse width (1.152 mbps) mir output width (0.576 mbps) 00000 0 ns 0 ns 00001 20.83 ns 41.66 ns 00010 41.66 (==20.83*2) ns 83.32 (==41.66*2) ns ... ... ... k 10 20.83* k 10 ns 41.66* k 10 ns ... ... ... 11111 645 ns 1290 ns set6.reg2 - sir pulse width reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sir_pw - - - s_pw4 s_pw3 s_pw2 s_pw1 s_pw0 reset value 0 0 0 0 0 0 0 0 this 5-bit register is set sir output pulse width. s_pw4~0 sir output pulse width 00000 3/16 bit time of uart 01101 1.6 us others 1.6 us set6.reg3 - set select register write this register then go to other set. read this register then return f0 16 . reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr ssr7 ssr6 ssr5 ssr4 ssr3 ssr2 srr1 srr0 default value 1 1 1 1 0 0 0 0 set6.reg4 - high speed infrared beginning flag number (hir_fnu) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hir_fnu m_fg3 m_fg2 m_fg1 m_fg0 f_fl3 f_fl2 f_fl1 f_fl0 reset value 0 0 1 0 1 0 1 0 bit 7~4: m_fg3~0 - mir beginning flag number these bits define the number of transmitter start flag of mir. note that the number of mir start flag should be equal or more than two which is defined in irda 1.1 physical layer. the default value is 2.
75 m_fg3~0 beginning flag number 0000 reserved 0001 1 0010 2 (default) 0011 3 0100 4 0101 5 0110 6 0111 8 1000 10 1001 12 1010 16 1011 20 1100 24 1101 28 1110 32 1111 reserved bit 3~0: f_fg3~0 - fir beginning flag numbe r these bits define the number of transmitter preamble flag in fir. note that the number of fir start flag should be equal to sixteen which is defined in irda 1.1 physical layer. the default value is 16. m_fg3~0 beginning flag number 0000 reserved 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 8 1000 10 1001 12 1010 16 (default) 1011 20 1100 24 1101 28 1110 32 1111 reserved
76 set7 - remote control and ir module selection registers address offset register name register description 0 rir_rxc remote infrared receiver control 1 rir_txc remote infrared transmitter control 2 rir_cfg remote infrared config register 3 ssr sets select register 4 irm_sl1 infrared module (front end) select 1 5 irm_sl2 infrared module select 2 6 irm_sl3 infrared module select 3 7 irm_cr infrared module control register set7.reg0 - remote infrared receiver control (rir_rxc) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rir_rxc rx_fr2 rx_fr1 rx_fr0 rx_fsl4 rx_fsl3 rx_fsl2 rx_fsl1 rx_fsl0 default value 0 0 1 0 1 0 0 1 this register defines frequency ranges of remote ir of receiver. bit 7~5: rx_fr2~0 - receiver frequency range 2~0 these bits select the input frequency of the receiver ranges. for the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. bit 4~0: rx_fsl4~0 - receiver frequency select 4~0 select the receiver operation frequency.
77 low frequency range select of receiver rx_fr2~0 (low frequency) 001 010 011 rx_fsl4~0 min. max. min. max. min. max. 00010 26.1 29.6 24.7 31.7 23.4 34.2 00011 28.2 32.0 26.7 34.3 25.3 36.9 00100 29.4 33.3 27.8 35.7 26.3 38.4 00101 30.0 34.0 28.4 36.5 26.9 39.3 00110 31.4 35.6 29.6 38.1 28.1 41.0 00111 32.1 36.4 30.3 39.0 28.7 42.0 01000 32.8 37.2 31.0 39.8 29.4 42.9 01001 33.6* 38.1* 31.7 40.8 30.1 44.0 01011 34.4 39.0 32.5 41.8 30.8 45.0 01100 36.2 41.0 34.2 44.0 32.4 47.3 01101 37.2 42.1 35.1 45.1 33.2 48.6 01111 38.2 43.2 36.0 46.3 34.1 49.9 10000 40.3 45.7 38.1 49.0 36.1 52n.7 10010 41.5 47.1 39.2 50.4 37.2 54.3 10011 42.8 48.5 40.4 51.9 38.3 56.0 10101 44.1 50.0 41.7 53.6 39.5 57.7 10111 45.5 51.6 43.0 55.3 40.7 59.6 11010 48.7 55.2 46.0 59.1 43.6 63.7 11011 50.4 57.1 47.6 61.2 45.1 65.9 11101 54.3 61.5 51.3 65.9 48.6 71.0 note that the other non-defined values are reserved. high frequency range select of receiver rx_fr2~0 (high frequency) 001 rx_fsl4~0 min. max. 00011 355.6 457.1 01000 380.1 489.8 01011 410.3 527.4 note that the other non-defined values are reserved. sharp ask-ir receiver frequency range select rx_fsl4~0 (sharp ask-ir) rx_fr2~0 001 010 011 100 101 110 - 480.0* 533.3* 457.1 564.7 436.4 600.0 417.4 640.0 400.0 685.6 384.0 738.5 note that the other non-defined values are reserved. set7.reg1 - remote infrared transmitter control (rir_txc) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rir_txc tx_pw2 tx_pw1 tx_pw0 tx_fsl4 tx_fsl3 tx_fsl2 tx_fsl1 tx_fsl0 default value 0 1 1 0 1 0 0 1
78 this register is defined the transmitter frequency and pulse width of remote ir. bit 7~5: tx_pw2~0 - transmitter pulse width 2~ 0 select the transmission pulse width. tx_pw2~0 low frequency high frequency 010 6 m s 0.7 m s 011 7 m s 0.8 m s 100 9 m s 0.9 m s 101 10.6 m s 1.0 m s note that the other non-defined tx_pw are reserved. bit 4~0: tx_fsl4~0 - transmitter frequency select 4~0 select the transmission frequency. low frequency selected tx_fsl4~0 low frequency 00011 30khz 00100 31khz ... ... 11101 56khz note that the other non-defined tx_fsl4~0 are reserved. high frequency selected tx_fsl4~0 high frequency 00011 400k hz 01000 450k hz 01011 480khz note that the other non-defined tx_fsl4~0 are reserved. set7.reg2 - remote infrared config register (rir_cfg) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rir_cfg p_pnb smp_m rxcfs - tx_cfs rx_dm tx_mm1 tx_mm0 default value 0 0 0 0 0 0 0 0 bit 7: p_pnb: programming pulse number coding write to 1 then programming pulse number coding is selected. the code format is defined as follows:
79 b7 b6 b5 b4 b2 b1 b0 b3 bit value (number of bits) - 1 the bit value is set to 0 , then the high pulse will be transmitted/received. the bit value is set to 1 , then no energy will be transmitted/received. bit 6: smp_m - sampling mode to choose receiver sampling mode. write to 0 then uses t-period sampling, that the t-period is programmed uart baud rate. write to 1 then directly use programmed baud rate to do over-sampling. bit 5: rxcfs - receiver carry frequency select rxcfs selected frequency 0 30k ~ 56khz 1 400k ~ 480khz bit 4: reserved, write 0. bit 3: tx_cfs - transmitter carry frequency select setting low speed or high speed transmitter carry frequency. tx_fcs selected frequency 0 30k ~ 56khz 1 400k ~ 480khz bit 2: rx_dm - receiver demodu lation mode rx_dm demodulation mode 0 enable internal decoder 1 disable internal decoder bit 1~0: tx_mm1~0 - transmitter modulation mode 1~0 tx_mm1~0 tx modulation mode 00 continuously send pulse for logic 0 01 8 pulses for logic 0 and no pulse for logic 1 10 6 pulses for logic 0 and no pulse for logic 1 11 reserved set7.reg3 - sets select register (ssr) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value 1 1 1 1 0 1 0 0 read this register and return f4 16 . write this register then switch to other set.
80 set7.reg4 - infrared module (front end) select 1 (irm_sl1) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irm_sl1 ir_msp sir_sl2 sir_sl1 sir_sl0 - air_sl2 air_sl1 air_sl0 default value 0 0 0 0 0 0 0 0 bit 7: ir_msp - ir mode select pulse write to 1, the transmitter (irtx) will send a 64 m s pulse to setup a special ir front-end operational mode. when ir front-end module uses mode select pin (md) and transmitter ir pulse (irtx) to switch high speed ir (such as fir or mir) or low speed ir (sir or ask-ir), this bit should be used. bit 6~4: sir_sl2~0 - sir (serial ir) mode select these bits are to program the operational mode of the sir front-end module. these values of sir_sl2~0 will automatically load to pins of ir_sl2~0, respectively, when (1) am_fmt=1 (automatic format, in set7.reg7.bit7), (2) the mode of advanced uart is set to sir (ad_md2~0, in set0.reg4.bit7~0). bit 3: reserved, write 0. bit 2~0: air_sl2~0 - ask-ir mode select these bits will setup the operational mode of ask-ir front-end module when am_fmt=1 and ad_md2~0 are set to ask-ir mode. these values will automatically load to ir_sl2~0, respectively. set7.reg5 - infrared module (front end) select 2 (irm_sl2) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irm_sl2 - fir_sl2 fir_sl1 fir_sl0 - mir_sl2 mir_sl1 mir_sl0 default value 0 0 0 0 0 0 0 0 bit 7: reserved, write 0. bit 6~4: fir_sl2~0 - fir mode select these bits setup the operational mode of f ir front-end module when am_fmt=1 and ad_md2~0 set to fir mode. these values will automatically load to ir_sl2~0, respectively. bit 3: reserved, write 0. bit 2~0: mir_sl2~0 - mir mode select these bits setup the mir operational mode when am_fmt=1 and a d_md2~0 set to mir mode. these values will be automatically loaded to ir_sl2~0, respectively.
81 set7.reg6 - infrared module (front end) select 3 (irm_sl3) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irm_sl3 - lrc_sl2 lrc_sl1 lrc_sl0 - hrc_sl2 hrc_sl1 hrc_sl0 default value 0 0 0 0 0 0 0 0 bit 7: reserved, write 0. bit 6~4: lrc_sl2~0 - low speed remote ir mode select these bits setup the operational mode of low speed remote ir front-end module when am_fmt=1 and ad_md2~0 set to remote ir mode. these values will automatically load to ir_sl2~0, respectively. bit 3: reserved, write 0. bit 2~0: hrc_sl2~0 - high speed remote ir mode select these bits setup the operational mode of high speed remote ir front-end module when am_fmt=1 and .ad_md2~0 set to remote ir mode. these values will automatically load to ir_sl2~0, respectively. set7.reg7 - infrared module control register (irm_cr) reg. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irm_cr am_fmt irx_msl irsl0d rxinv txinv - - - default value 0 0 0 0 0 0 0 0 bit 7: am_fmt - automatic format write to 1 , enable automatic format ir front-end module. these bit will affect the output of ir_sl2~0 which is referred by ir front-end module selection (set7.reg4~6) bit 6: irx_msl - ir receiver modu le select select the receiver input path from the ir front end module if ir module has the separated high speed and low speed receiver path. if the ir module is only one receiving path, then this bit should be set to 0. irx_msl receiver pin selected 0 irrx (low/high speed) 1 irrxh (high speed) bit 5: irsl0d - direction of irsl0 pin select function for irrxh or irsl0 because they are common pin and different input/output direction. irsl0_d function 0 irrxh (i/p) 1 irsl0 (o/p)
82 ir receiver input pin selection irsl0d irx_msl aux_rx high speed ir selected ir pin 0 0 0 x irrx 0 0 1 x irrxh 0 1 x 0 irrx 0 1 x 1 irrxh 1 0 0 x irrx 1 0 1 x reserved 1 1 x 0 irrx 1 1 x 1 reserved note that (1) aux_rx is defined in set5.reg4.bit4, (2) high speed ir includes mir (1.152 or 0.576 mbps) and fir (4 mbps), (3) irrx is the input of the low speed or high speed ir receiver, irrxh is the input of the high speed ir receiver. bit 4: rxinv - receiving signal invert write to 1, invert the receiving signal. bit 3: txinv - transmitting signal invert write to 1, invert the transmitting signal. bit 2~0: reserved, write 0.
83 parallel port printer interface logic the parallel port of the FDC87W21 makes possible the attachment of various devices that accept eight bits of parallel data at standard ttl level. the FDC87W21 supports an ibm xt/at compatible parallel port (spp), bi-directional parallel port (bpp), enhanced parallel port (epp), extended capabilities parallel port (ecp), extension fdd mode (extfdd), extension 2fdd mode (ext2fdd), extension adapter mode (extadp), and joystick mode on the parallel port. refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation. table 2a shows the pin definitions for different modes of the parallel port. table 2a - parallel port connnector and pin definition for spp/epp/ecp modes host connector FDC87W21 pin number pin attribute spp epp ecp 1 19 o nstb nwrite nstb, hostclk 2-9 9-14,16-17 i/o pd<0:7> pd<0:7> pd<0:7> 10 26 i nack intr nack, periphclk 11 24 i busy nwait busy, periphack 2 12 27 i pe pe peerror, nackreverse 2 13 28 i slct select slct, xflag 14 20 o nafd ndstrb nafd, hostack 2 15 29 i nerr nerror nfault 1 , nperiphrequest 2 16 21 o ninit ninit ninit 1 , nreverserqst 2 17 22 o nslin nastrb nslin 1 , ecpmode 2 notes: n : active low 1. compatible mode 2. high speed mode 3. for more information, refer to the ieee 1284 standard. table 2b - parallel port connector and pin definition for extfdd and ext2fdd modes host connector FDC87W21 pin number pin attribute spp pin attribute ext2fdd pin attribute extfdd 1 19 o nstb --- --- --- --- 2 9 i/o pd0 i nindex2 i nindex2 3 10 i/o pd1 i ntrak02 i 4 11 i/o pd2 i nwp2 i 5 12 i/o pd3 i nrdata2 i nrdata2 6 13 i/o pd4 i ndskchg2 i ndskchg2 7 14 i/o pd5 --- --- --- --- 8 15 i/o pd6 od nmoa2 --- --- 9 16 i/o pd7 od ndsa2 --- ---
84 host connector FDC87W21 pin number pin attribute spp pin attribute ext2fdd pin attribute extfdd 10 26 i nack od ndsb2 od 11 24 i busy od nmob2 od 12 27 i pe od nwd2 od nwd2 13 28 i slct od nwe2 od nwe2 14 20 o nafd od nrwc2 od nrwc2 15 29 i nerr od nerr2 od 16 21 o ninit od ndir2 od ndir2 17 22 o nslin od nstep2 od 6 13 i/o pd4 i ndskchg2 i ndskchg2 7 14 i/o pd5 --- --- --- --- 8 15 i/o pd6 od nmoa2 --- --- 9 16 i/o pd7 od ndsa2 --- --- 10 26 i nack od ndsb2 od 11 24 i busy od nmob2 od 12 27 i pe od nwd2 od nwd2 13 28 i slct od nwe2 od nwe2 14 20 o nafd od nrwc2 od nrwc2 15 29 i nerr od nnerr2 od 16 21 o ninit od ndir2 od ndir2 17 22 o nslin od nstep2 od table 2c - parallel port connector and pin definition for extadp mode host connector FDC87W21 pin number pin attribute spp pin attribute extadp mode pin attribute joystick mode 1 19 o nstb o nxwr o vdd 2 9 i/o pd0 i/o xd0 i jp0 3 10 i/o pd1 i/o xd1 i jp1 4 11 i/o pd2 i/o xd2 i --- 5 12 i/o pd3 i/o xd3 i --- 6 13 i/o pd4 i/o xd4 i jb0 7 14 i/o pd5 i/o xd5 i jb1 8 15 i/o pd6 i/o xd6 i --- 9 16 i/o pd7 i/o xd7 i --- 10 26 i nack i xdrq i --- 11 24 i busy i xirq i --- 12 27 i pe o xa0 i --- 13 28 i slct o xa1 i --- 14 20 o nafd o nxrd o vdd 15 29 i nerr o xa2 i --- 16 21 o ninit o nxdack o vdd 17 22 o nslin o tc o vdd
85 enhanced parallel port (epp) table 3 - printer mode and epp register address a2 a1 a0 register note 0 0 0 data port (r/w) 1 0 0 1 printer status buffer (read) 1 0 1 0 printer control latch (write) 1 0 1 0 printer control swapper (read) 1 0 1 1 epp address port (r/w) 2 1 0 0 epp data port 0 (r/w) 2 1 0 1 epp data port 1 (r/w) 2 1 1 0 epp data port 2 (r/w) 2 1 1 1 epp data port 2 (r/w) 2 notes: 1. these registers are available in all modes. 2. these registers are available only in epp mode. data swapper the system microprocessor can read the contents of the printer's data latch by reading the data swapper. printer status buffer the system microprocessor can read the printer status by reading the address of the printer status buffer. the bit definitions are as follows: bit 7: this signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state. when this signal is active, the printer is busy and cannot accept data. bit 6: this bit represents the current state of the printer's nack signal. a 0 means the printer has received a character and is ready to accept another. normally, this signal will be active for approximately 5 microseconds before nbusy stops. bit 5: a 1 means the printer has detected the end of paper. bit 4: a 1 means the printer is selected. bit 3: a 0 means the printer has encountered an error condition. tmout nerror 1 1 1 2 3 5 4 6 7 0 slct pe nbusy nack
86 bit 1, 2: these two bits are not implemented and are logic one during a read of the status register. bit 0: this bit is valid in epp mode only. it indicates that a 10 m s time-out has occurred on the epp bus. a logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. printer control latch and printer control swapper the system microprocessor can read the contents of the printer control latch by reading the printer control swapper. bit definitions are as follows: bit 7, 6: these two bits are a logic one during a read. they can be written. bit 5: direction control bit when this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). this bit can be read and written. in spp mode, this bit is invalid and fixed at zero. bit 4: a 1 in this position allows an interrupt to occu r when nack changes from low to high. bit 3: a 1 in this bit position selects the printer. bit 2: a 0 starts the printer ( 50 microsecond pulse, minimum). bit 1: a 1 causes the printer to line-feed after a line is printed. bit 0: a 0.5 microsecond minimum high active pulse clocks data into the printer. valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 1 1 1 2 3 4 5 6 7 0 strobe auto fd slct in irq enable dir ninit
87 epp address port the address port is available only in epp mode. bit definitions are as follows: 1 2 3 4 5 6 7 0 pd0 pd1 pd2 pd3 pd5 pd4 pd6 pd7 the contents of db0-db7 are buffered (non-inverting) and output to ports pd0-pd7 during a write operation. the leading edge of niow causes an epp address write cycle to be performed, and the trailing edge of niow latches the data for the duration of the epp write cycle. pd0-pd7 ports are read during a read operation. the leading edge of nior causes an epp address read cycle to be performed and the data to be output to the host cpu. epp data port 0-3 these four registers are available only in epp mode. bit definitions of each data port are as follows: 1 2 3 4 5 6 7 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 when accesses are made to any epp data port, the contents of db0-db7 are buffered (non-inverting) and output to the ports pd0-pd7 during a write operation. the leading edge of niow causes an epp data write cycle to be performed, and the trailing edge of niow latches the data for the duration of the epp write cycle. during a read operation, ports pd0-pd7 are read, and the leading edge of nior causes an epp read cycle to be performed and the data to be output to the host cpu.
88 bit map of parallel port and epp registers register 7 6 5 4 3 2 1 0 data port (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 status buffer (read) nbusy nack pe slct nerror 1 1 tmout control swapper (read) 1 1 1 irqen slin ninit nautofd nstrobe control latch (write) 1 1 dir irq slin ninit nautofd nstrobe epp address port (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 0 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 1 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 2 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp data port 3 (r/w) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 epp pin descriptions epp name type epp description nwrite o denotes an address or data read or write operation. pd<0:7> i/o bi-directional epp address and data bus. intr i used by peripheral device to interrupt the host. nwait i inactive to acknowledge that data transfer is completed. active to indicate that the device is ready for the next transfer. pe i paper end ; same as spp mode. select i printer selected status ; same as spp mode. ndstrb o this signal is active low. it denotes a data read or write operation. nerror i error ; same as spp mode. ninits o this signal is active low. when it is active, the epp device is reset to its initial operating mode. nastrb o this signal is active low. it denotes an address read or write operation. epp operation when the epp mode is selected in the configuration register, the standard and bi- directional modes are also available. the pdx bus is in the standard or bi-directional mode when no epp read, write, or address cycle is currently being executed. in this condition all output signals are set by the spp control port and the direction is controlled by dir of the control port. a watchdog timer is required to prevent system lockup. the timer indicates that more than 10 m s have elapsed from the start of the epp cycle to the time nwait is de-asserted. the current epp cycle is aborted when a time-out occurs. the time-out condition is indicated in status bit 0. epp operation the epp operates on a two-phase cycle. first, the host selects the register within the device for subsequent operations. second, the host performs a series of read and/or write byte operations to the selected register. four operations are supported on the epp: address write, data write, address read, and data read. all operations on the epp device are performed asynchronously. epp version 1.9 operation the epp read/write operation can be completed under the following conditions: (a) if the nwait is active low, when the read cycle (nwrite inactive high, ndstrb/nastrb active low) or write cycle (nwrite active low, ndstrb/nastrb active low) starts, the read/write cycle proceeds normally and
89 will be completed when nwait goes inactive high. (b) if nwait is inactive high, the read/write cycle will not start. it must wait until nwait changes to active low, at which time it will start as described above. epp version 1.7 operation the epp read/write cycle can start without checking whether nwait is active or inactive. once the read/write cycle starts, however, it will not terminate until nwait changes from active low to inactive high. extended capabilities parallel (ecp) port this port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ecp is not required. it provides an automatic high burst-bandwidth channel that supports dma for ecp in both the forward (host to peripheral) and reverse (peripheral to host) directions. small fifos are used in both forward and reverse directions to improve the maximum bandwidth requirement. the size of the fifo is 16 bytes. the ecp port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the ecp port supports run-length-encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. hardware support for compression is optional. for more information about the ecp protocol, refer to the extended capabilities port protocol and isa interface standard.
90 ecp register and mode definitions name address i/o ecp modes function data base+000h r/w 000-001 data register ecpafifo base+000h r/w 011 ecp fifo (address) dsr base+001h r all status register dcr base+002h r/w all control register cfifo base+400h r/w 010 parallel port data fifo ecpdfifo base+400h r/w 011 ecp fifo (data) tfifo base+400h r/w 110 test fifo cnfga base+400h r 111 configuration register a cnfgb base+401h r/w 111 configuration register b ecr base+402h r/w all extended control register note: the base addresses are specified by cr23, which are determined by configuration register or hardware setting. mode description 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the cr9 and cr0 to select ecp/epp mode) 101 reserved 110 test mode 111 configuration mode note: the mode selection bits are bit 7-5 of the extended control register.
91 data and ecpafifo port modes 000 (spp) and 001 (ps/2) (data port) during a wite operation, the data register latches the contents of the data bus on the rising edge of the input. the contents of this register are output to the pd0-pd7 ports. during a read operation, ports pd0-pd7 are read and output to the host. the bit definitions are as follows: 7 6 5 4 3 2 1 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 mode 011 (ecp fifo-address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peripheral automatically. the operation of this register is defined only for the forward direction. the bit definitions are as follows: 7 6 5 4 3 2 1 0 address or rle address/rle device status register (dsr) these bits are at low level during a read of the printer status register. the bits of this status register are defined as follows: 7 6 5 4 3 2 1 0 nfault select perror nack nbusy 1 1 1 bit 7: this bit reflects the complement of the busy input. bit 6: this bit reflects the nack input.
92 bit 5: this bit reflects the perror input. bit 4: this bit reflects the select input. bit 3: this bit reflect s the nfault input. bit 2-0: these three bits are not implemented and are always logic one during a read. device control register (dcr) the bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 strobe autofd ninit select in direction ackint en bit 6, 7: these two bits are logic one during a read and cannot be written. bit 5: this bit has no effect and the direction is always out if mode = 000 or mode = 010. direction is valid in all other modes. 0 the parallel port is in output mode. 1 the parallel port is in input mode. bit 4: interrupt r equest enable. when this bit is set to a high level, it may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the nack input. bit 3: this bit is inverted and output to the nslin output. 0 the printer is not selected. 1 the printer is selected. bit 2: this bit is output to the ninit output. bit 1: this bit is inverted and output to the nafd output. bit 0: this bit is inverted and output to the nstb output. cfifo (parallel port data fifo) mode = 010 this mode is defined only for the forward direction. the standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or dmaed from the system to this fifo. transfers to the fifo are byte aligned.
93 ecpdfifo (ecp data fifo) mode = 011 when the direction bit is 0, bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. when the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ecp into this fifo. reads or dmas from the fifo will return bytes of ecp data to the system. tfifo (test fifo mode) mode = 110 data bytes may be read, written, or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the parallel port lines. however, data in the tfifo may be displayed on the parallel port data lines. cnfga (configuration register a) mode = 111 this register is a read-only register. when it is read, 10h is returned. this indicates to the system that this is an 8-bit implementation. cnfgb (configuration register b) mode = 111 the bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 1 intrvalue compress irqx 0 irqx 1 irqx 2 bit 7: this bit is read-only. it is at low level during a read. this means that this chip does not support hardware rle compression. bit 6: returns the value on the isa irq line to determine possible conflicts. bit 5-3: reflect the irq resourc e assigned for ecp port. cnfgb[5:3] irq resource 000 reflect other irq resources selected by pnp register (default) 001 irq7 010 irq9 011 irq10 100 irq11 101 irq14 110 irq15 111 irq5 bit 2-0: these five bits are at high level during a read and can be written.
94 ecr (extended control register) mode = all this register controls the extended ecp parallel port functions. the bit definitions are follows: 7 6 5 4 3 2 1 0 empty full service intr dma en nerrintr en mode mode mode bit 7-5: thes e bits are read/write and select the mode. 000 standard parallel port mode. the fifo is reset in this mode. 001 ps/2 parallel port mode. this is the same as 000 except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. 010 parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data are automatically transmitted using the standard parallel port protocol. this mode is useful only when direction is 0. 011 ecp parallel port mode. when the direction is 0 (forward direction), bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. when the direction is 1 (reverse direction) bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. 100 selects epp mode. in this mode, epp is active if the epp supported option is selected. 101 reser ved. 110 test mode. the fifo may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 configuration mode. the confga and confgb registers are accessible at 0x400 and 0x401 in this mode. bit 4: read/write (valid only in ecp mode) 1 disables the interrupt generated on the asserting edge of nfault. 0 enables an interrupt pulse on the high to low edge of nfault. if nfault is asserted (interrupt) an interrupt will be generated and this bit is written from a 1 to 0. bit 3: read/write 1 enables dma. 0 disables dma unconditionally. bit 2: read/write
95 1 disables dma and all of the service interrupts. 0 enables one of the following cases of interrupts. when one of the service interrupts has occurred, the serviceintr bit is set to a 1 by hardware. this bit must be reset to 0 to re-enable the interrupts. writing a 1 to this bit will not cause an interrupt. (a) dmaen = 1: during dma this bit is set to a 1 when terminal count is reached. (b) dmaen = 0 direction = 0: this bit is set to 1 whenever there are writeintr threshold or more bytes free in the fifo. (c) dmaen = 0 direction = 1: this bit is set to 1 whenever there are readintr threshold or more valid bytes to be read from the fifo. bit 1: read only 0 the fifo ha s at least 1 free byte. 1 the fifo cannot accept another byte or the fifo is completely full. bit 0: read only 0 the fifo contains at least 1 byte of data. 1 the fifo is completely empty. bit map of ecp port registers d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nbusy perror select nfault 1 1 1 1 dcr 1 1 directio ackinten selectin ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue 1 1 1 1 1 1 ecr mode nerrintren dmaen serviceintr full empty notes: 1. these registers are available in all modes. 2. all fifos use one common 16-byte fifo.
96 ecp pin descriptions name type description nstrobe (hostclk) o the nstrobe registers data or address into the slave on the asserting edge during write operations. this signal handshakes with busy. pd<7:0> i/o these signals contains address or data or rle data. nack (periphclk) i this signal indicates valid data driven by the peripheral when asserted. this signal handshakes with nautofd in reverse. busy (periphack) i this signal deasserts to indicate that the peripheral can accept data. it indicates whether the data lines contain ecp command information or data in the reverse direction. when in reverse direction, normal data are transferred when busy (periphack) is high and an 8-bit command is transferred when it is low. perror (nackreverse) i this signal is used to acknowledge a change in the direction of the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select (xflag) i indicates printer on line. nautofd (hostack) o requests a byte of data from the peripheral when it is asserted. this signal indicates whether the data lines contain ecp address or data in the forward direction. when in forward direction, normal data are transferred when nautofd (hostack) is high and an 8-bit command is transferred when it is low. nfault (nperiphrequest) i generates an error interrupt when it is asserted. this signal is valid only in the forward direction. the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer during ecp mode. ninit (nreverserequest) o this signal sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. nselectin (ecpmode) o this signal is always deasserted in ecp mode.
97 ecp operation the host must negotiate on the parallel port to determine if the peripheral supports the ecp protocol before ecp operation. after negotiation, it is necessary to initialize some of the port bits. the following are required: 1. set direction = 0, enabling the drivers. 2. set strobe = 0, causing the nstrobe signal to default to the deasserted state. 3. set autofd = 0, causing the nautofd signal to default to the deasserted state. 4. set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo, respectively. mode switching software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (mode 011 or 010). if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can be changed only in mode 001. when in extended forward mode, the software should wait for the fifo to be empty before switching back to mode 000 or 001. in ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. command/data ecp mode allows the transfer of normal 8-bit data or 8-bit commands. in the forward direction, normal data are transferred when hostack is high and an 8-bit command is transferred when hostack is low. the most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address. in the reverse direction, normal data are transferred when periphack is high and an 8-bit command is transferred when periphack is low. the most significant bit of the command is always zero. data compression the FDC87W21 supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. note that the odd (rle) compression in hardware is not supported. in order to transfer data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. fifo operation the fifo threshold is set in configuration register 5. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode, as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. after a reset, the fifo is disabled. dma transfers dma transfers are always to or from the ecpdfifo, tfifo, or cfifo. the dma uses the standard pc dma services. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and serviceintr is asserted, which will disable the dma. programmed i/o (non-dma) mode the ecp or parallel port fifos can also be operated using interrupt driven programmed i/o. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. the host must set the direction, state, dmaen = 0 and serviceintr = 0 in the programmed i/o transfers.
98 the ecp requests programmed i/o transfers from the host by activating the irq pin. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. extension fdd mode (extfdd) in this mode, the FDC87W21 changes the printer interface pins to fdc input/output pins, allowing the user to install a second floppy disk drive (fdd b) through the db-25 printer connector. the pin assignments for the fdc input/output pins are shown in table 2. after the printer interface is set to extfdd mode, the following occur: 1. pins nmob and ndsb will be forced to inactive state. 2. pins ndskchg, nrdata, nwp, ntrak0, nindex will be logically ored with pins pd4-pd0 to serve as input signals to the fdc. 3. pins pd4-pd0 each will have an internal resistor of about 1k ohm to serve as pull-up resistor for fdd open drain/collector output. 4. if the parallel port is set to extfdd mode after the system has booted dos or another operating system , a warm reset is needed to enable the system to recognize the extension floppy drive. extension 2fdd mode (ext2fdd) in this mode, the FDC87W21 changes the printer interface pins to fdc input/output pins, allowing the user to install two external floppy disk drives through the db-25 printer connector to replace internal floppy disk drives a and b. the pin assignments for the fdc input/output pins are shown in table 2. after the printer interface is set to extfdd mode, the following occur: 1. pins nmoa, ndsa, nmob, and ndsb will be forced to inactive state. 2. pins ndskchg, nrdata, nwp, ntrak0, and nindex will be logically ored with pins pd4-pd0 to serve as input signals to the fdc. 3. pins pd4-pd0 each will have an internal resistor of about 1k ohm to serve as pull-up resistor for fdd open drain/collector output. 4. if the parallel port is set to ext2fdd mode after the system has booted dos or another operating system , a warm reset is needed to enable the system to recognize the extension floppy drive. extension adapter mode (extadp) (patent pending) in this mode, the FDC87W21 redefines the printer interface pins for use as an extension adapter, allowing a pocket peripheral adapter card to be installed through the db-25 printer connector. the pin assignments for the extension adapter are shown in table 2. xdo-xd7 are the system data bus for the extension adapter. xa0-xa2 are the system address bus. nxwr and nxrd are the i/o read/write commands with address comparing match or in dma access mode. nxdack, xtc, and xdrq are used in conjunction with npdackx, tc, and pdrqx to execute a dma cycle. the extension adapter can issue a dma request by setting pin xdrq high, thus sending the FDC87W21 output to the host system by pin pdrqx. the dma controller should recognize the dma request and output a relative dack to pin npdackx of the FDC87W21, which will output the dack without any change from pin nxdack to the extension adapter. once the dma transfer is completed, a terminal count (tc) should be issued from the dma controller to pin tc of FDC87W21 and output to the extension adapter via pin xtc. xirq is the interrupt request of the extension adapter. the value of xirq coming from the extension adapter will directly pass through pin irq7 to the host system.
99 xirq and irq7, nxdackandnpdackx, and xdrq and pdrqx are three input/output pairs of FDC87W21 pins. although these pins are defined as dma and interrupt functions, they can be redefined by users for other specific functions. operation the idea behind extadp mode is to treat the parallel port db-25 connector as an isa slot, except that its addresses are not issued to the extension adapter. the operation of extadp mode is described below: 1. set the FDC87W21 to extadp mode by programming bit 7 of cr7 as low and bit 3 and bit 2 of cr0 as high and low, respectively. 2. the FDC87W21 cr2 is an address register that records the address of the extension adapter. when the desired address is written into cr2, pins nxwr and nxrd of the FDC87W21 will simultaneously go low and the desired address will also appear on the printer data bus pd7-pd0. users can logically or these two signals as an initial reset. 3. after the above two steps, every time the host system issues an ior or iow command, the FDC87W21 will compare the i/o address with the cr2 register. if the comparison matches, the data, low bits addresses (xa2-xa0), and nxwr/nxrd will be presented on the parallel port db-25 connector. 4. dma operations are handled in the same way as item 3, except that the relevant npdackx, pdrqx will be active on the db- 25 connector. joystick mode (patent pending) the joystick mode allows users to plug a joystick into the parallel port db-25 connector. the pin definitions are shown in table 2. pins nnstb, nafd, nnslin, and ninit output high as a voltage supply to the joystick. pins pd5 and pd4 are the button input of the joystick. pins pd1 and pd0 are the x/y axis paddle input of the joystick. there are two one-shot timers (556) inside the FDC87W21 for use with the joystick.
100 game port decoder the FDC87W21 provides ngmrd and ngmwr pins that decode game port address as specified in cr1e and i/o read/write commands. if the host issues nior and the specified address, the ngmrd pin is low active; if it issues niow and the specified address, the ngmwr pin is low active. plug and play configuration a powerful new plug-and-play function has been built into the FDC87W21 to help simplify the task of setting up a computer environment. with appropriate support from bios manufacturers, the system designer can freely allocate smsc i/o devices (i.e., the fdc, prt, uart, ide, and game port) in the pc's i/o space (100h - 3ffh). in addition, the FDC87W21 also provides 8 interrupt requests and 3 dma pairs for designers to assign in interfacing fdcs, uarts, and prts. hence this powerful i/o chip offers greater flexibility for system designers. the pnp feature is implemented through a set of extended function registers (cr1e and cr20 to 29). details on configuring these registers are given in section 8. the default values of these pnp-related registers set the system to a configuration compatible with environments designed with previous smsc i/o chips. extended function registers the FDC87W21 provides many configuration registers for setting up different types of configurations. after power-on reset, the state of the hardware setting of each pin will be latched by the relevant configuration register to allow the FDC87W21 to enter the proper operating configuration. to protect the chip from invalid reads or writes, the configuration registers cannot be accessed by the user. there are four ways to enable the configuration registers to be read or written. hefere (cr0c bit 5) and hefras (cr16 bit 0) can be used to select one out of these four methods of entering the extended function mode as follows: hefras hefere address and value 0 0 write 88h to the location 250h 0 1 write 89h to the location 250h (power-on default) 1 0 write 86h to the location 3f0h twice 1 1 write 87h to the location 3f0h twice first, a specific value must be written once (88h/89h) or twice (86h/87h) to the extended functions enable register (i/o port address 250h or 3f0h). second, an index value (00h- 17h, 1eh, 20h-29h) must be written to the extended functions index register (i/o port address 251h or 3f0h) to identify which configuration register is to be accessed. the designer can then access the desired configuration register through the extended functions data register (i/o port address 252h or 3f1h). after programming of the configuration register is finished, an additional value should be written to efers to exit the extended function mode to prevent unintentional access to those configuration registers. in the case of efer at 250h, this additional value can be any value other than 88h if hefere = 0 and 89h if hefere = 1. while efer is at 3f0h, this
101 additional value must be aah. the designer can also set bit 6 of cr9 (lockreg) to high to protect the configuration registers against accidental accesses. the configuration registers can be reset to their default or hardware settings only by a cold reset (pin mr = 1). a warm reset will not affect the configuration registers. extended functions enable registers (efers) after a power-on reset, the FDC87W21 enters the default operating mode. before the FDC87W21 enters the extended function mode, a specific value must be programmed into the extended function enable register (efer) so that the extended function register can be accessed. the extended function enable registers are write-only registers. on a pc/at system, their port addresses are 250h or 3f0h (as described in the above section). extended function index registers (efirs), extended function data registers (efdrs) after the extended function mode is entered, the extended function index register (efir) must be loaded with an index value (0h, 1h, 2h, or 29h) to access configuration register 0 (cr0), configuration register 1 (cr1), configuration register 2 (cr2), and so forth through the extended function data register (efdr). the efirs are write-only registers with port address 251h or 3f0h (as described in section 8.0) on pc/at systems; the efdrs are read/write registers with port address 252h or 3f1h (as described in section 8.0) on pc/at systems. the function of each configuration register is described below.
102 configuration register 0 (cr0), default = 00h when the device is in extended function mode and efir is 0h, the cr0 register can be accessed through efdr. the bit definitions for cr0 are as follows: 7 6 5 4 3 2 1 0 ocss0 ocss1 reserved reserved reserved reserved prtmods0 prtmods1 bit 7-bit 4 : reserved. prtmod1 prtmod0 (bit 3, bit 2): these two bits and prtmod2 (cr9 bit7) determine the parallel port mode of the FDC87W21 (as shown in the following table). prtmods2 (bit 7 of cr9) prtmod1 (bit 3 of cr0) prtmods0 (bit 2 of cr0) 0 0 0 spp 0 0 1 extfdc 0 1 0 extadp 0 1 1 ext2fdd 1 0 0 joystick 1 0 1 epp/spp 1 1 0 ecp 1 1 1 ecp/epp 00 spp mode (default), prtmod2 = 0; standard and bi-directional modes 01 extension fdd mode (extfdd), prtmod2 = 0 10 extension adapter mode (extadp), prtmod2 = 0 11 extension 2fdd mode (ext2fdd), prtmod2 = 0 00 joystick mode, prtmod2 = 1 01 epp mode and spp mode, prtmod2 = 1 10 ecp mode, prtmod2 = 1 11 ecp mode and epp mode, prtmod2 = 1 oscs1, oscs0 (bit 1, bit 0): these two bits and oscs2 (cr6 bit 6) are used to select one of the FDC87W21's power-down functions. these bits may be programmed in four different ways: 00 default power-on state after power-on reset (oscs2 = 0). 00 osc on, 24 mhz clock is stopped internally (oscs2 = 1). clock can be restarted by clearing oscs2. 01 immediate power-down (ipd) state, oscs2 = 0
103 when bit 0 is 1 and bit 1 is set to 0, the FDC87W21 will stop its oscillator and enter power-down mode immediately. the FDC87W21 will not leave the power-down mode until either a system power-on reset from the mr pin or these two bits are used to program the chip back to power-on state. after leaving the power-down mode, the FDC87W21 must wait 128 ms for the oscillator to stabilize. 10 standby for automatic power-down (apd), oscs2 = 0 when bit 1 is set to 1 and bit 0 is set to 0, the FDC87W21 will stand by for automatic power-down. a power-down will occur when the following conditions obtain: fdc not busy fdd motor off interrupt source of line status, modem status, and data ready is inactive (neglecting ier enable/disable) master reset inactive souta and soutb in idle state sina and sinb in idle state no register read or write to chip if all of these conditions are met, a counter begins to count down. while the timer is counting down, the FDC87W21 remains in normal operating mode, and if any of the above conditions changes, the counter will be reset. if the set time (set by bit 7 and bit 6 of cr8) elapses without a change in any of the above conditions, bits 1 and 0 will be set to (1, 1) and the chip will enter automatic power-down mode. the oscillator of the FDC87W21 will remain running, but the internal clock will be disabled to save power. once the above conditions are no longer met, the internal clock will be re-supplied and the chip will return to normal operation. 11 automatic power-down (adp) state, oscs2 = 0 the FDC87W21 enters this state automatically after the counter described above has counted down. if there is a change in any of the conditions listed above, the FDC87W21 's clock will be restarted and bits 1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. when the clock is restarted, the chip is ready for normal operation, with no need to wait for the oscillator to stabilize.
104 configuration register 1 (cr1), default = 00h when the device is in extended function mode and efir is 01h, the cr1 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved abchg bit 0-bit 6: reserved. abchg (bit 7): this bit enables the fdc ab change mode. default to be enabled at power-on reset. 0 drives a and b assigned as usual 1 drive a and drive b assignments exchanged configuration register 2 (cr2), default = 00h when the device is in extended function mode and efir is 02h, the cr2 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 cea ea3 ea4 ea5 ea6 ea7 ea8 ea9 when the FDC87W21 is programmed into extension adapter mode, the contents of this register are a base address for the extension adapter. when base addresses ea3-ea9 are written into cr2, both the nxrd and nxwr pins will be active low simultaneously and an adapter connected to the parallel port can latch the same base address through pins xd1-xd7. after the base address is latched into cr2, a subsequent read/write cycle to this same base address will generate an nxrd or nxwr signal. if cea is set to 0, then the FDC87W21 will compare system addresses sa9-sa3 with ea9-ea3 to generate a compare-equal signal for this read/write command to access the extension adapter. if cea is set to 1, then only ea9-ea4 are used in this comparison.
105 configuration register 3 (cr3), default = 30h when the device is in extended function mode and efir is 03h, the cr3 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 submidi suamidi reserved reserved gmods eppver gmenl reserved submidi (bit 0): this bit selects the clock divide rate of uart b. 0 disables midi support, uart b clock = 24 mhz divided by 13 (default) 1 enabl es midi support, uart b clock = 24 mhz divided by 12 suamidi (bit 1): this bit selects the clock divide rate of uart a. 0 disables midi support, uart a clock = 24 mhz divided by 13 (default) 1 enables midi support, uart a clock = 24 mhz divided by 12 bit 2-bit 3 : reserved. gmods (bit 4): this bit selects the adapter mode or portable mode. 0 selects the portable mode. pins 41 and 39 will function as pfdcen and pexten 1 selects the adapter mode. pins 41 and 39 will function as ngmrd and ngmwr note: gmdrq (cr16 bit 3) has higher precedence over this bit. that is, gmods selection is only valid when gmgrq = 1. eppver (bit 5): this bit selects the epp version of parallel port: 0 selects the epp 1.9 version 1 selects the epp 1.7 version (default) bit 7-bit 6 : reserved.
106 configuration register 4 (cr4), default = 00h when the device is in extended function mode and efir is 04h, the cr4 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 urbtri uratri gmtri prttri urbpwd urapwd gmpwd prtpwd prtpwd (bit 7): 0 supplies power to the parallel port (default) 1 puts the parallel port in power-down mode gmpwd (bit 6): 0 supplies power to the game port (default) 1 puts the game port in power-down mode urapwd (bit 5): 0 supp lies power to coma (default) 1 puts coma in power-down mode urbpwd (bit 4): 0 supplies power to comb (default) 1 puts comb in power-down mode prttri (bit 3): this bit enables or disables the tri-state outputs of parallel port in power-down mode. 0 the output pins of the parallel port will not be tri-stated when parallel port is in power-down mode. ( default) 1 the output pins of the parallel port will be tri-stated when parallel port is in power- down mode. gmtri (bit 2): this bit enables or disables the tri-state outputs of the game port in power-down mode. 0 the output pins of the game port will not be tri-stated when game port is in power- down mode. ( default) 1 the output pins of the game port will be tri-stated when game port is in power -down mode.
107 uratri (bit 1): this bit enables or disables the tri-state outputs of uart a in power-down mode. 0 the output pins of uart a will not be tri-stated when uart a is in power-down mode. 1 the output pins of uart a will be tri-stated when uart a is in power-down mode. urbtri (bit 0): this bit enables or disables the tri-state outputs of uart b in power-down mode. 0 the output pins of uart b will not be tri-stated when uart b is in power-down mode. 1 the output pins of uart b will be tri-st ated when uart b is in power-down mode. configuration register 5 (cr5), default = 00h when the device is in extended function mode and efir is 05h, the cr5 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 ecpfthr0 ecpfthr1 ecpfthr2 reserved reserved reserved reserved ecpfthr3 bit 7-4: reserved ecpfthr3-0 (bit 3-0): these four bits define the fifo threshold for the ecp mode parallel port. the default value is 0000 after power-up. configuration register 6 (cr6), default = 00h when the device is in extended function mode and efir is 06h, the cr6 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 fdctri idepwd fdcpwd fipurdwm sel4fdd oscs2 reserved idetri bit 7: reserved oscs2 (bit 6): this bit and oscs1, oscs0 (bit 1, 0 of cr0) select one of the FDC87W21's power- down functions. refer to descriptions of cr0. (default to be 0)
108 sel4fdd (bit 5): selects four fdd mode 0 selects two fdd mode (default, see table 4) 1 selects four fdd mode ndsa, ndsb, nmoa and nmob output pins are encoded as show in table 5 to select four drives. table 4 do register ( 3f2h ) drive bit 7 bit 6 bit 5 bit 4 bit 1 bit 0 n mob n moa n dsb n dsa selected 0 0 0 0 0 0 1 1 1 1 -- 0 0 0 1 0 0 1 0 1 0 fdd a 0 0 1 0 0 1 0 1 0 1 fdd b 0 1 0 0 0 1 1 1 1 1 -- 1 0 0 0 1 1 1 1 1 1 -- table 5 do register ( 3f2h ) drive bit 7 bit 6 bit 5 bit 4 bit 1 bit 0 n mob n moa n dsb n dsa selected 0 0 0 0 x x 1 1 x x -- 0 0 0 1 0 0 0 0 0 0 fdd a 0 0 1 0 0 1 0 0 0 1 fdd b 0 1 0 0 1 0 0 0 1 0 fdd c 1 0 0 0 1 1 0 0 1 1 fdd d fipurdwn (bit 4): this bit controls the internal pull-up resistors of the fdc input pins nrdata, nindex, ntrak0, ndskchg, and nwp. 0 the internal pull-up resistors of fdc are turned on. (default) 1 the internal pull-up resistors of fdc are turned off.
109 fdcpwd (bit 3): this bit controls the power to the fdc. 0 power is supplied to the fdc. ( default) 1 puts the fdc in power-down mode. idepwd (bit 2): this bit controls the power of the ide. 0 power is supplied to the ide. ( default) 1 puts the ide in power-down mode. fdctri (bit 1): this bit enables or disables the tri-state outputs of the fdc in power-down mode. 0 the output pins of the fdc will not be tri-stated when fdc is in power-down mode. 1 the output pins of the fdc will be tri-stated when fdc is in p ower-down mode. idetri (bit 0): this bit enables or disables the tri-state outputs of the ide in power-down mode. 0 the output pins of the ide will not be tri-stated when ide is in power-down mode. 1 the output pins of the ide will be tri-stated when ide is in power-down mode. configuration register 7 (cr7), default = 00h when the device is in extended function mode and efir is 07h, the cr7 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 fdd a type 0 fdd a type 1 fdd b type 0 fdd b type 1 fdd c type 0 fdd c type 1 fdd d type 0 fdd d type 1 fdd a type 1, 0 (bit 1, 0): these two bits select the type of fdd a. 00 selects normal mode. when nrwc = 0, the data transfer rate is 250 kb/s. when nrwc= 1, the data transfer rate is 500 kb/s. three mode fdd select (en3mode = 1 ; bit 5 of cr9 = 1): 01 n rwc = 0, selects 1.2 mb high-density fdd. 10 nrwc = 1, selects 1.44 mb high-density fdd. 11 don't care nrwc, selects 720 kb double-density fdd. fdd b type 1, 0 (bit 3, 2): these two bits select the type of fdd b. 00 selects normal mode. when nrwc = 0, the data transfer rate is 250 kb/s. when nrwc= 1, the data transfer rate is 500 kb/s.
110 three mode fdd select (en3mode = 1): 01 nrwc = 0, selects 1.2 mb high-density fdd. 10 nrwc = 1, selects 1.44 mb high-density fdd. 11 don't care nrwc, selects 720 kb double-density fdd. fdd c type 1, 0 (bit 5, 4): these two bits select the type of fdd c. 00 selects normal mode. when nrwc = 0, the data transfer rate is 250 kb/s. when nrwc = 1, he data transfer rate is 500 kb/s. three mode fdd select (en 3 mode = 1): 01 nrwc = 0, selects 1.2 mb high-density fdd. 10 nrwc = 1, selects 1.44 mb high-density fdd. 11 don't care nrwc, selects 720 kb double-density fdd. fdd d type 1, 0 (bit 7, 6): these two bits select the type of fdd d. 00 selects normal mode. when nrwc = 0, the data transfer rate is 250 kb/s. when nrwc = 1, the data transfer rate is 500 kb/s. three mode fdd select (en3mode = 1): 01 nrwc = 0, selects 1.2 mb high-density fdd. 10 nrwc = 1, selects 1.44 mb high-density fdd. 11 don't care nrwc, selects 720 kb double-density fdd. configuration register 8 (cr8), default = 00h when the device is in extended function mode and efir is 08h, the cr8 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 floppy boot drive 0 floppy boot drive 1 media id 0 media id 1 disfddwr apdtms2 apdtms1 swwp apdtms2 apdtms1 (bit 6, 7): these two bits select the count-down time of the automatic power-down mode counter. 00 4 seconds 01 32 seconds 10 64 seconds 11 4 minutes
111 disfddwr (bit 5): this bit enables or disables fdd write data. 0 enables fdd write 1 disables fdd write (forces pins nwe, nwd to stay high) once this bit is set high, the fdc operates normally, but because pin nwe is inactive, the fdd will not write data to diskettes. for example, if a diskette is formatted with disfddwr = 1, after the format command has been executed, messages will be displayed that appear to indicate that the format is complete. if the diskette is removed from the disk drive and inserted again, however, typing the dir command will reveal that the contents of the diskette have not been modified and the diskette was not actually reformatted. this is because as the operating system (e.g., dos) reads the diskette files, it keeps the files in memory. if there is a write operation, dos will write data to the diskette and memory simultaneously. when dos wants to read the diskette, it will first search the files in memory. if dos finds the file in memory, it will not issue a read command to read the diskette. when disfddwr = 1, dos still writes data to the diskette and memory, but only the data in memory are updated. if a read operation is performed, data are read from memory first, and not from the diskette. the action of removing the diskette from the drive and inserting it again forces the ndskchg pin active. dos will then read the contents of the diskette and will show that the contents have not been modified. the same holds true with write commands. the disable fdd write function allows users to protect diskettes against computer viruses by ensuring that no data are written to the diskette. swwp (bit 4): 0 normal, use nwp to determine whether the fdd is write-protected or not 1 fdd is always write-protected media id 1 media id 0 (bit 3, 2): these two bits hold the media id bit 1, 0 for three mode floppy boot drive 1 floppy boot drive 0 (bit 1, 0) these two bits hold the value of floppy boot drive 1 and drive 0 for three mode
112 configuration register 9 (cr9), default = 0ah when the device is in extended function mode and efir is 09h, the cr9 register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 chip id0 chip id1 chip id2 chip id3 reserved lockreg en3mode prtmods2 prtmods2 (bit 7): this bit and prtmods1, prtmods0 (bits 3, 2 of cr0) select the operating mode of the FDC87W21. refer to the descriptions of cr0. lockreg (bit 6): this bit enables or disables the reading and writing of all configuration registers. 0 enables the reading and writing of cr0-cr29 1 disables the reading and writing of cr0-cr29 (locks FDC87W21 extension functions) en3mode (bit 5): this bit enables or disables three mode fdd selection. when this bit is high, it enables the read/write 3f3h register. 0 disables 3 mode fdd selection 1 enables 3 mode fdd selection when three mode fdd function is enabled, the value of nrwc depends on bit 5 and bit 4 of tdr(3f3h). the values of nrwc and their meaning are shown in table 6. table 6 bit 5 of tdr bit 4 of tdr n rwc n rwc = 0 n rwc = 1 0 0 normal 250kbps 500kbps 0 1 0 1.2 m fdd x 1 0 1 x 1.4m fdd 1 1 x x x bit 4: reserved. chip id 3, chip id 2, chip id 1, chip id 0 (bit 3-0): these four bits are read-only bits that contain chip identification information. the value is 0bh for FDC87W21 during a read.
113 configuration register a (cra), default = 1fh when the device is in extended function mode and efir is 0ah, the cra register can be accessed through efdr. the bit definitions are as follows: 7 6 5 4 3 2 1 0 pextecpp pext ecp pext epp pext adp pext act pdcact pdirhop pfdcact pfdcact (bit 7): this bit controls whether pfdcen (pin 41) is active high or low in portable mode. 0 pfdcen is active low 1 pfdcen is active high pextact (bit 6): this bit controls whether pexten (pin 39) is active high or low in portable mode. this pin can also reflect the mode of the parallel port: extadp mode, epp mode, ecp mode, or ecp/epp mode, or any combination of these modes. 0 pexten is active low 1 pexten is active high bit 5: reserved. pdcact (bit 4): this bit controls whether the pdcin pin is active high or low. 0 pdcin is active low 1 pdcin is active high pextadp (bit 3): this bit controls whether the pexten pin is active in extadp mode. 0 pexten is not active in extadp mode 1 pexten is active in extadp mode pextepp (bit 2): this bit controls whether the pexten pin is active in epp mode. 0 pexten is not active in epp mode 1 pexten is active in epp mode pextecp (bit 1): this bit controls whether the pexten pin is active in ecp mode. 0 pexten is not active in ecp mode 1 pexten is active in ecp mode
114 pextecpp (bit 0): this bit controls whether the pexten pin is active in ecp/epp mode. 0 pexten is not active in ecp/epp mode 1 pexten is active in ecp/epp mode configuration register b (cr0b), default = 0ch when the device is in extended function mode and efir is 0bh, the crb register can be accessed through efdr. the bit definitions are as follows: bit 7: dsprtpu 0 enable parallel port pull-up resister. 1 disable parallel port pull-up resister. txw4c (bit 6): this bit is active high. when active, the ir controller will wait for 4-character period of time from the end of last receiving before it can start transmitting data. rxw4c (bit 5): this bit is active high. when active, the ir controller will wait for 4-character period of time from the end of last transmitting before it can start receiving data. enifchg (bit 4): this bit is active high. when active, it enables host interface mode change, which is determined by ident (bit 3) and mfm (bit 2). ident (bit 3): this bit indicates the type of drive being accessed and changes the level on nrwc (pin 87). 0 nrwc will be active low for high data rates (typically used for 3.5" drives) 1 nrwc will be active high for high data rates (typically used for 5.25" drives) 1 2 3 4 5 6 7 0 ndrv2en invertz ident enifchg mfm rxw4c txw4c reserved
115 when hardware reset or enifchg is a logic 1, ident and mfm select one of three interface modes, as shown in table 7. table 7 ident mfm interface 0 0 model 30 mode 0 1 ps/2 mode 1 0 at mode 1 1 at mode mfm (bit 2): this bit and ident select one of the three interface modes (ps/2 mode, model 30, or pc/at mode). intvertz (bit 1): this bit determines the polarity of all fdd interface signals. 0 fdd interface signals are active low 1 fdd interface signals are active high ndrvden (bit 0): ps/2 mode only when this bit is a logic 0, indicates a second drive is installed and is reflected in status register a. configuration register c (cr0c), default = 28h when the device is in extended function mode and efir is 0ch, the cr0c register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 tx2inv rx2inv reserved urirsel enbkirsl hefere turb tura tura (bit 7): 0 the clock source of uart a is 1.8462 mhz (24 mhz divide 13) (default) 1 the clock source of uart a is 24 mhz, it can make the baud rate of uart a up to 1.5 mhz turb (bit 6): 0 the clock source of uart b is 1.84 62 mhz (24 mhz divide 13) (default) 1 the clock source of uart b is 24 mhz, it can make the baud rate of uart a up to 1.5 mhz hefere (bit 5): this bit combines with hefras (cr16 bit 0) to define how to enable extended function registers.
116 hefras hefere address and value 0 0 write 88h to the location 250h 0 1 write 89h to the location 250h (default) 1 0 write 86h to the location 3f0h twice 1 1 write 87h to the location 3f0h twice the default value of hefere is 1. bit 4: enbkirsl - enable bank ir function select. 0 ir selection of configuration register is higher priority. 1 ir selection of bank of uart b is higher priority. urirsel (bit 3): 0 select uart b as ir function. 1 select uart b as normal function. the default value of urirsel is 1. bit 2: reserved. rx2inv (bit 1): 0 the sinb pin of uart b function or irrx pin of ir function in normal condition. 1 inverse the sinb pin of uart b function or irrx pin of ir function tx2inv (bit 0): 0 the soutb pin of uart b functi on or irtx pin of ir function in normal condition. 1 inverse the soutb pin of uart b function or irtx pin of ir function. configuration register d (cr0d), default = a3h when the device is in extended function mode and efir is 0dh, the cr0d register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 sirtx1 sirtx0 sirrx1 sirrx0 hduplx irmode2 irmode1 irmode0 sirtx1 (bit 7): irtx pin selection bit 1 sirtx0 (bit 6): irtx pin selection bit 0 sirtx1 sirtx0 irtx output on pin 0 0 disabled 0 1 irtx1 (pin 43) 1 0 irtx2 (pin 95) 1 1 disabled
117 sirrx1 (bit 5): irrx pin selection bit 1 sirrx0 (bit 4): irrx pin selection bit 0 sirrx1 sirrx0 irrx input on pin 0 0 disabled 0 1 irrx1 (pin 42) 1 0 irrx2 (pin 94) 1 1 disabled hduplx (bit 3): 0 the ir function is full duplex. 1 the ir function is half duplex. irmode2 (bit 2): ir function mode selection bit 2 irmode1 (bit 1): ir function mode selection bit 1 irmode0 (bit 0): ir function mode selection bit 0 ir mode ir function irtx irrx 00x disable tri-state high 010* irda active pulse 1.6 m s demodulation into sinb 011* irda active pulse 3/16 bit time demodulation into sinb 100 ask-ir inverting irtx pin routed to sinb 101 ask-ir inverting irtx & 500 khz clock routed to sinb 110 ask-ir inverting irtx demodulation into sinb 111* ask-ir inverting irtx & 500 khz clock demodulation into sinb note: the notation is normal mode in the ir function. the sir schematic diagram for registers crc and crd is shown below.
118 configuration register e (cr0e), configuration register f (cr0f) reserved for testing. should be kept all 0's. 1 0 1 mux 0 1 0 01 00 10 11 11,00 01 10 1 mux 0 1 mux 0 1 0 mux irda mod. 3/16 irda mod. mod1.6u irda irmode0 irmode2 (crd.bit2) urirsel (crc,bit3) transmission time frame 16550a sin uart2 sout rx2inv (crc.bit1) urirsel (crc.bit3) 1 0 mux sirrx1~0 cr0d.bit5,4 ask_ir sin2 irmode1 (crd.bit3) huplx irmode0 (crd.bit0) 500khz mux mux (crd.bit1) irmode2 (crd.bit2) irmode2,1=00 (crd.bit0) disable irtx1 irtx2 sout2 ncs1 irrx1 irrx2 +5v ncs0 +5v sirtx1~0 crd.bit7,6 tx2inv crc.bit0 mux mux ir-da demodulation demodulation (default) (default) configuration register 10 (cr10), default = 00h when the device is in extended function mode and efir is 10h, the cr10 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 gio0ad7 gio0ad0 gio0ad1 gio0ad2 gio0ad3 gio0ad4 gio0ad5 gio0ad6 gio0ad7-gio0ad0 (bit 7-bit 0): giop0 (pin 92 ) address bit 7 - bit 0.
119 configuration register 11 (cr11), default = 00h when the device is in extended function mode and efir is 11h, the cr11 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 g0cadm1 gio0ad8 gio0ad9 gio0ad10 reserved g0cadm0 reserved reserved g0cadm1-g0cadm0 (bit 7-bit 6): giop0 address bit compare mode selection g0cadm1 g0cadm0 giop0 pin 0 0 compare gio0ad10-gio0ad0 with sa10-sa0 0 1 compare gio0ad10-gio0ad1 with sa10-sa1 1 0 compare gio0ad10-gio0ad2 with sa10-sa2 1 1 compare gio0ad10-gio0ad3 with sa10-sa3 bit 5-bit 3: reserved gio0ad10-gio0ad8 (bit 2-bit 0): giop0 (pin 92) address bit 10-bit 8 configuration register 12 (cr12), default = 00h when the device is in extended function mode and efir is 12h, the cr12 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 gio1ad7 gio1ad0 gio1ad1 gio1ad2 gio1ad3 gio1ad4 gio1ad5 gio1ad6 gio1ad7-gio1ad0 (bit 7-bit 0): giop1 (pin 96 ) address bit 7-bit 0.
120 configuration register 13 (cr13), default = 00h when the device is in extended function mode and efir is 13h, the cr13 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 g1cadm1 gio1ad8 gio1ad9 gio1ad10 reserved g1cadm0 reserved reserved g1cadm1-g1cadm0 (bit 7-bit 6): giop1 address bit compare mode selection g1cadm1 g1cadm0 giop1 pin 0 0 compare gio1ad10-gio1ad0 with sa10-sa0 0 1 compare gio1ad10-gio1ad1 with sa10-sa1 1 0 compare gio1ad10-gio1ad2 with sa10-sa2 1 1 compare gio1ad10-gio1ad3 with sa10-sa3 bit 5- bit 3: reserved gio1ad10-gio1ad8 (bit 2-it 0): giop1 (pin 96) address bit 10-bit 8 configuration register 14 (cr14), default = 00h when the device is in extended function mode and efir is 14h, the cr14 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 gda0ipi gda0opi gcs0iow gcs0ior gio0csh giop0md0 giop0md1 giop0md2 giop0md2-giop0md0 (bit 7-bit 5): giop0 pin mode selection
121 giop0md2 giop0md1 giop0md0 giop0 pin 0 0 0 0 0 1 inactive (tri-state) as a data output pin (sd0 ? giop0), when (aen = l) and (niow = l) and (sa10-0 = gio0ad10-0), the value of sd0 will be present on giop0 0 1 0 as a data input pin (giop0 ? sd0), when (aen = l) and (nior = l) and (sa10-0 = gio0ad10- 0), the value of giop0 will be present on sd0 0 1 1 as a data input/output pin (giop0 ? sd0). when (aen = l) and (niow = l) and (sa10-0 = gio0ad10-0), the value of sd0 will be present on giop0 when (aen = l) and (nior = l) and (sa10-0 = gio0ad10-0), the value of giop0 will be present on sd0 1 x x as a chip select pin, the pin will be active at (aen = l) and (sa10-0 = gio0ad10-0) or (nior = l) or (niow = l) gio0csh(bit 4): 0 the chip select pin will be active low when (aen = l) and (sa10-0 = gio0ad10-0) or (nior = l) or (niow = l) 1 the chip select pin will be active high when (aen = l) and (sa10-0 = gio0ad10-0) or (nior = l) or (niow = l) gcs0ior (bit 3): see below. gcs0iow (bit 2): see below. gcs0ior gcs0iow 0 0 giop0 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio0ad10-0) 0 1 giop0 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio0ad10-0) and (niow = l) 1 0 giop0 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio0ad10-0) and (nior = l) 1 1 giop0 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio0ad10-0) and (niow = l or nior = l)
122 gda0opi (bit 1): see below. gda0ipi (bit 0): see below. gda0opi gda0ipi 0 0 giop0 functions as a data pin, and giop0 ? sd0, sd0 ? giop0 0 1 giop0 functions as a data pin, and inverse giop0 ? sd0, sd0 ? giop0 1 0 giop0 functions as a data pin, and giop0 ? sd0, inverse sd0 ? giop0 1 1 giop0 functions as a data pin, and inverse giop0 ? sd0, inverse sd0 ? giop0 configuration register 15 (cr15), default = 00h when the device is in extended function mode and efir is 15h, the cr15 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 gda0ipi gda0opi gcs0iow gcs0ior gio0csh giop0md0 giop0md1 giop0md2 giop1md2-giop1md0 (bit 7-bit 5): giop1 pin mode selection giop1md2 giop1md1 giop1md0 giop1 pin 0 0 0 inactive (tri-state) 0 0 1 as a data output pin (sd1 ? giop1), when (aen = l) and (niow = l) and (sa10-0 = gio1ad10-0), the value of sd1 will be present on giop1 0 1 0 as a data input pin (giop1 ? sd1), when (aen = l) and (nior = l) and (sa10-0 = gio1ad10-0), the value of giop1 will be present on sd1 0 1 1 as a data input/output pin (giop1 ? sd1). when (aen = l) and (niow = l) and (sa10-0 = gio1ad10-0), the value of sd1 will be present on giop1 when (aen = l) and (nior = l) and (sa10-0 = gio1ad10-0), the value of giop1 will be present on sd1 1 x x as a chip select pin, the pin will be active at (aen = l) and (sa10-0 = gio1ad10-0) or (nior = l) or (niow = l)
123 gio1csh (bit 4): 0 the chip select pin will active low when (aen = l) and (sa10-0 = gioad10- 0) or (nior = l) or (niow = l) 1 the chip select pin will active high when (aen = l) and (sa10-0 = gioad10- 0) or (nior = l) or (niow = l) gcs1ior (bit 3): see below. gcs1iow (bit 2): see below. gcs1ior gcs1iow 0 0 giop1 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio1ad10-0) 0 1 giop1 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio1ad10-0) and (niow = l) 1 0 giop1 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio1ad10-0) and (nior = l) 1 1 giop1 functions as a chip select pin, and will be active when (aen = l) and (sa10-0 = gio1ad10-0) and (niow =l or nior = l) gda0opi (bit 1): see below. gda1ipi (bit 0): see below. gda1opi gda1ipi 0 0 giop1 functions as a data pin, and giop1 ? sd1, sd1 ? giop1 0 1 giop1 functions as a data pin, and inverse giop1 ? sd1, sd1 ? giop1 1 0 giop1 functions as a data pin, and giop1 ? sd1, inverse sd1 ? giop1 1 1 giop1 functions as a data pin, and inverse giop1 ? sd1, inverse sd1 ? giop1
124 configuration register 16 (cr16), default = 0eh when the device is in extended function mode and efir is 16h, the cr16 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 hefras iride pnpcvs gmdrq goiqsel reserved reserved reserved bit 7-bit 4: reserved. g1qasel (bit 5): 0 pin 96 function as irq_a. 1 pin 96 function as gio1. the corresponding power-on setting pin is nrtsb (pin 45). g0qbsel (bit 4): 0 pins 92 function as irq_b. 1 pins 92 function as gio0. the corresponding power-on setting pin is nrtsb (pin 45). gmdrq (bit 3): 0 pins 39, 41 function as drq_a, ndack_a, respectively. 1 pins 39, 41 function as ngmwr, ngmrd, respectively. the corresponding power-on setting pin is soutb (pin 43). pnpcvs (bit 2): 0 pnp-related registers (cr1e, cr20-29) reset to be all 0s. 1 default settings for these registers.
125 the corresponding power-on setting pin is nrtsa (pin 36). pnp register pnpcvs = 1 pnpcvs = 0 cr1e 81h 00h cr20 fch 00h cr21 7ch 00h cr22 fdh 00h cr23 deh 00h cr24 feh 00h cr25 beh 00h cr26 23h 00h cr27 05h 00h cr28 43h 00h cr29 60h 00h note: the new value of pnpcvs must be complementary to the old one to make an effective change. for example, the user must set pnpcvs to 1 first and then reset it to 0 to reset these pnp registers if the present value of pnpcvs is 0. iride (bit 1): 0 pins 1, 91, 94, 95 function as ide ports. 1 pins 1, 91, 94, 95 function as ir ports. the corresponding power-on setting pin is souta (pin 38). pin iride = 0 iride = 1 1 nrstide irq_g 91 nidben irq_h 94 ncs0 irrx2 95 ncs1 irtx2 hefras (bit 0): combines with hefere (cr0c bit 5) to define how to access extended function registers (refer to cr0c bit 5 description). the corresponding power-on setting pin is ndtra (pin 35). configuration register 17 (cr17), default = 00h when the device is in extended function mode and efir is 17h, the cr17 register can be accessed through efdr. the bit definitions are as follows: 1 2 3 4 5 6 7 0 dsublgrq dsualgrq dsprlgrq dsfdlgrq prirqod reserved reserved reserved
126 bit 7-bit 5: reserved. prirqod (bit4): 0 printer irq ports are totem-poles in spp mode and open-drains in ecp/epp mode. 1 printer irq ports are totem-poles in all modes. dsfdlgrq (bit 3): 0 enable fdc legacy mode on irq and drq selections. do register bit 3 has effect on selecting irq. 1 disable fdc legacy mode on irq and drq selections. do register bit 3 has no effect on selecting irq. dsprlgrq (bit 2): 0 enable prt legacy mode on irq and drq selections. dcr bit 4 has effect on selecting irq. 1 disable prt legacy mode on irq and drq selections. dcr bit 4 has no effect on selecting irq. dsualgrq (bit 1): 0 enable uart a legacy mode on irq selection. mcr bit 3 has effect on selecting irq. 1 disable uart a legacy mode on irq selection. mcr bit 3 has no effect on selecting irq. dsublgrq (bit 0): 0 enable uart b legacy mode on irq selection. mcr bit 3 has effect on selecting irq. 1 disable uart b legacy mode on irq selection. mcr bit 3 has no effect on selecting irq.
127 configuration register 1e (cr1e) when the device is in extended function mode and efir is 1eh, the cr1e register can be accessed through efdr. default = 81h if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 gmas0 gmas1 gmad2 gmad3 gmad4 gmad5 gmad6 gmad7 this register is used to select the base address of game chip select decoder (gamecs) from 100h- 3f0h on 16-byte boundaries. ncs = 0 and a10 = 0 are required to qualify the gamecs output. gmad7-gmad2 (bit 7-bit 2): match a[9:4]. gmas1-gmas0 (bit 1-bit 0): camecs configuration. 00 gamecs disable 01 1-byte decode, a[3:0] = 0001b 10 8-byte decode, a[3:0] = 0xxxb 11 16-byte decode, a[3:0] = xxxxb configuration register 20 (cr20) when the device is in extended function mode and efir is 20h, the cr20 register can be accessed through efdr. default = fch if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved reserved fdcad2 fdcad3 fdcad4 fdcad5 fdcad6 fdcad7 this register is used to select the base address of the floppy disk controller (fdc) from 100h-3f0h on 16-byte boundaries. ncs = 0 and a10 = 0 are required to access the fdc registers. a[3:0] are always decoded as 0xxxb. fdcad7-fdcad2 (bit 7-bit 2): match a[9:4]. bit 7 = 0 and bit 6 = 0 disable this decode. bit 1-bit 0: reserved, fixed at zero.
128 configuration register 21 (cr21) when the device is in extended function mode and efir is 21h, the cr21 register can be accessed through efdr. default = 7ch if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved reserved ide0ad2 ide0ad3 ide0ad4 ide0ad5 ide0ad6 ide0ad7 this register is used to select the base address of the ide interface control registers from 100h- 3f0h on 16-byte boundaries. ncs = 0 and a10 = 0 are required to access the ide registers. a[3:0] are always decoded as 0xxxb. ide0ad7-ide0ad2 (bit 7-bit 2): match a[9:4]. bit 7 = 0 and bit 6 = 0 disable this decode. bit 1-bit 0: reserved, fixed at zero. configuration register 22 (cr22) when the device is in extended function mode and efir is 22h, the cr22 register can be accessed through efdr. default = fdh if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved reserved ide1ad2 ide1ad3 ide1ad4 ide1ad5 ide1ad6 ide1ad7 this register is used to select the base address of the ide interface alternate status register from 106h-3f6h on 16-byte boundaries + 6. ncs = 0 and a10 = 0 are required to access the ide alternate status register. a[3:0] must be 0110b. ide1ad7-ide1ad2 (bit 7-bit 2): match a[9:4]. bit 7 = 0 and bit 6 = 0 disable this decode. bit 1: reserved, fixed at zero. bit 0: reserved, fixed at one.
129 configuration register 23 (cr23) when the device is in extended function mode and efir is 23h, the cr23 register can be accessed through efdr. default = deh if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 prtad0 prtad1 prtad2 prtad3 prtad4 prtad5 prtad6 prtad7 this register is used to select the base address of the parallel port. if epp is disable, the parallel port can be set from 100h-3fch on 4-byte boundaries. if epp is enable, the parallel port can be set from 100h-3f8h on 8-byte boundaries. ncs = 0 and a10 = 0 are required to access the parallel port when in compatible, bi-directional, or epp modes. a10 is active in ecp mode. prtad7-prtad0 (bit 7-bit 0): match a[9:2]. bit 7 = 0 and bit 6 = 0 disable this decode. configuration register 24 (cr24) when the device is in extended function mode and efir is 24h, the cr24 register can be accessed through efdr. default = feh if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved uraad1 uraad2 uraad3 uraad4 uraad5 uraad6 uraad7 this register is used to select the base address of the uart a from 100h-3f8h on 8-byte boundaries. ncs = 0 and a10 = 0 are required to access the uart a registers. a[2:0] are don't-care conditions. uraad7-uraad1 (bit 7-bit 1): match a[9:3]. bit 7 = 0 and bit 6 = 0 disable this decode. bit 0: reserved, fixed at zero.
130 configuration register 25 (cr25) when the device is in extended function mode and efir is 25h, the cr25 register can be accessed through efdr. default = beh if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved urbad1 urbad2 urbad3 urbad4 urbad5 urbad6 urbad7 this register is used to select the base address of the uart b from 100h-3f8h on 8-byte boundaries. ncs = 0 and a10 = 0 are required to access the uart b registers. a[2:0] are don't-care conditions. urbad7-urbad1 (bit 7-bit 1): match a[9:3]. bit 7 = 0 and bit 6 = 0 disable this decode. bit 0: reserved, fixed at zero. configuration register 26 (cr26) when the device is in extended function mode and efir is 26h, the cr26 register can be accessed through efdr. default = 23h if cr16 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 prtdqs0 prtdqs1 prtdqs2 prtdqs3 fdcdqs0 fdcdqs1 fdcdqs2 fdcdqs3 fdcdqs3-fdcdqs0 (bit 7-bit 4): allocate dma resource for fdc. prtdqs3-prtdqs0 (bit 3-bit 0): allocate dma resource for prt. bit 7- bit4, bit 3 - bit 0 dma selected 0000 none 0001 dma_a 0010 dma_b 0011 dma_c
131 configuration register 27 (cr27) when the device is in extended function mode and efir is 27, the cr27 register can be accessed through efdr. default = 05h if cr6 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 prtiqs0 prtiqs1 prtiqs2 prtiqs3 reserved ecpirqx0 ecpirqx1 ecpirqx2 ecpirqx2-ecpirqx0 (bit7-bit 5): these bits are configurable equivalents to bit[5:3] of cnfgb register in ecp mode except that cnfgb[5:3] are read-only bits. they indicate the irq resource assigned for the ecp printer port. it is the software designer's responsibility to ensure that cr27[7:5] and cr27[3:0] are consistent. for example, cr27[7:5] should be filled with 001 (select irq 7) if cr27[3:0] are to be programmed as 0101 (select irq_e) while irq_e is connected to irq 7. cr27[7:5] irq resource 000 reflect other irq resources selected by cr27[3:0] (default) 001 irq 7 010 irq 9 011 irq 10 100 irq 11 101 irq 14 110 irq 15 111 irq 5 bit 4: reserved. prtiqs3-prtiqs0 (bit 3-bit 0): select irq resource for the parallel port. any unselected irq is in tristate. cr27[3:0] irq selected 0000 none 0001 irq_a 0010 irq_b 0011 irq_c 0100 irq_d 0101 irq_e 0110 irq_f 0111 irq_g 1000 irq_h
132 configuration register 28 (cr28) when the device is in extended function mode and efir is 28, the cr28 register can be accessed through efdr. default = 43h if cr6 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 urbiqs0 urbiqs1 urbiqs2 urbiqs3 uraiqs0 uraiqs1 uraiqs2 uraiqs3 uraiqs3-uraiqs0 (bit 7-bit 4): allocate interrupt resource for uart a. urbiqs3-urbiqs0 (bit 3-bit 0): allocate interrupt resource for uart b. configuration register 29 (cr29) when the device is in extended function mode and efir is 29, the cr29 register can be accessed through efdr. default = 62h if cr6 bit 2 = 1 ; default = 00h if cr16 bit 2 = 0. the bit definitions are as follows: 1 2 3 4 5 6 7 0 iqniqs0 iqniqs1 iqniqs2 iqniqs3 fdciqs0 fdciqs1 fdciqs2 fdciqs3 fdciqs3-fdciqs0 (bit 7-bit 4): allocate interrupt resource for fdc. iqniqs3-iqniqs0 (bit 3-bit 0): allocate interrupt resource for irqin. configuration registers (cr2a) when the device is in extended function mode and efir is 2ah, the cr2a register can be accessed through efdr. this register default value is 00 16 . the bit definitions are as follows: 1 2 3 4 5 6 7 0 irrxdrqsl0 irrxdrqsl1 irrxdrqsl2 irrxdrqsl3 irtxdrqsl0 irtxdrqsl1 irtxdrqsl2 irtxdrqsl3 irtxdrqsl (bit 7-bit 4): transmitter dma channel a through d selection when high speed infrared (fir/mir) is used and enable dma channel. note that these bits is used in two dma channels.
133 irrxdrqsl (bit 3-bit 0): receiver or transmitter dma channel a through selection when high speed infrared (fir/mir) is used and enable dma channel. note that these bits act as rx dma channel selection if two dma channel is used, or these bits act as rx/tx dma channel selection if single dma channel is used. configuration registers (cr2b) when the device is in extended function mode and efir is 2bh, the cr2b register can be accessed through efdr. this register default value is 00 16 . the bit definitions are as follows: 1 2 3 4 5 6 7 0 pin93fun0 pin93fun1 pin3fun0 pin3fun1 pin2fun0 pin2fun1 pin1fun0 pin1fun1 bit 7~6: pin1fun1~0 - pin 1 function select. pin1fun1 pin1fun0 pin 1 0 0 irq_g 0 1 nreside 1 0 drq_d 1 1 irsl2 bit 5-4: pin2fun1~0 - pin 2 function select. pin2fun1 pin2fun0 pin 2 0 0 ncs 0 1 ndack_d 1 0 irsl1 1 1 irsl2 bit 3-2: pin3fun1~0 - pin 3 function select. pin3fun1 pin3fun0 pin 3 0 0 pdcin 0 1 ndack_d 1 0 irsl1 1 1 irrxh/irsl0
134 bit 1-0: pin93fun1~0 - pin 93 function select. pin93fun1 pin93fun0 pin 93 0 0 irqin 0 1 drq_d 1 0 irsl2 1 1 irrxh/irsl0 configuration registers (cr2c) when the device is in extended function mode and efir is 2ch, the cr2c register can be accessed through efdr. this register default value is 10 16 . the bit definitions are as follows: 1 2 3 4 5 6 7 0 reserved emulfun clkinsel enbnksel apedcrc pin91fun0 pin91fun1 pin91fun2 bit 7- 5 : pin91fun2~0 - pin 91 function select. pin91fun(cr2c.7) pin91fun(cr2c.6) pin91fun(cr2c.5) pin 91 0 0 0 irq_h 0 0 1 ndbenl 0 1 0 irsl2 0 1 1 irrxh/irsl0 1 0 0 dack_d note: the irsl0/irrxh selection is determined by bit 5(irsl0 mode selection) of register 7 of bank 7. when setting bit 5 to logical 1, irsl0 is selected; when setting bit 5 to logical 0, irrxh is selected. bit 4 :apedcrc - append crc to receiver when a frame is end. = 0 no append hardware crc value as data in fir/mir mode = 1 append hardware crc value as data in fir/mir mode bit 3 :enbnksel - bank select enable = 0 disable uart b bank selection = 1 enable uart b bank selection bit 2 :clkinsel - clock input selection = 0 the clock on pin xtal1/xtal2 is 24 mhz = 1 the clock on pin xtal1/xtal2 is 48 mhz bit 1:emulfun - emulate internal defined function = 0 disable emulation mode = 1 enable emulation mode bit 0: reserved.
135 configuration registers (cr2d) when the device is in extended function mode and efir is 2d 16 , the cr2d register can be accessed through efdr. this register default value is 00 16 . the bit definitions are as follows: 1 2 3 4 5 6 7 0 drta0 drta1 dis_precomp0 drtb0 drtb1 dis_precomp1 reserved reserved this register controls the data rate selection for fdc. it also controls if pre-compensation is enabled. drta1, drta0 (bit 1 - bit 0): these two bits combining with data rate selection bits in data rate register select the operational data rate for fdd a as follows: drive rate table data rate operational data rate drta1 drta0 drate1 drate0 mfm fm 0 0 1 1 1m --- 0 0 0 0 500k 250k 0 0 0 1 300k 150k 0 0 1 0 250k 125k 0 1 1 1 1m --- 0 1 0 0 500k 250k 0 1 0 1 500k 250k 0 1 1 0 250k 125k 1 0 1 1 1m --- 1 0 0 0 500k 250k 1 0 0 1 2m --- 1 0 1 0 250k 125k
136 dis_precomp0 (bit 2): this bit controls if pre-compensation is enabled for fdd a. 0 enable pre-compensatio n for fdd a 1 disable pre-compensation for fdd a drtb1, drtb0 (bit 4 - bit 3): these two bits combining with data rate selection bits in data rate register select the operational data rate for fdd b as shown in last table. dis_precomp1 (bit 5): this bit controls if precompensation is enabled for fdd b. 0 enable precompensation for fdd b 1 disable precompensation for fdd b bit 7 - bit 6: reserved.
137 bit map configuration registers table 8 - bit map of configuration registers register power-on reset value d7 d6 d5 d4 cr0 0000 0000 0 0 0 0 cr1 0000 0000 abchg 0 0 0 cr2 0000 0000 ra9 ra8 ra7 ra6 cr3 0011 0000 0 gmenl eppver gmods cr4 0000 0000 prtpwd gmpwd urapwd urbpwd cr5 0000 0000 0 0 0 0 cr6 0000 0000 0 oscs2 sel4fdd fipurdwn cr7 0000 0000 fdd d t1 fdd d t0 fdd c t1 fdd c t0 cr8 0000 0000 apdtms1 apdtms0 disfddwr swwp cr9 0000 1011 prtmods2 lockreg en3mode 0 cra 0001 1111 pfdcact pextact pdirhisop pdchact crb 0000 0000 0 tx4wc rx4wc enifchg crc 0010 1000 tura turb hefere enbkirsl crd 1010 0011 sirtx1 sirtx0 sirrx1 sirrx0 cr10 0000 0000 gio0ad7 gio0ad6 gio0ad5 gio0ad4 cr11 0000 0000 0 0 0 0 cr12 0000 0000 gio1ad7 gio1ad6 gio1ad5 gio1ad4 cr13 0000 0000 0 0 0 0 cr14 0000 0000 giop0md2 giop0md1 giop0md0 gio0csh cr15 0000 0000 giop1md2 giop1md1 giop1md0 gio1csh cr16 000s ssss 1 0 0 g1qasel g0qbsel cr17 0000 0000 0 0 0 prirqod cr1e 1000 0001 2 gmad7 gmad6 gmad5 gmad4 cr20 1111 1100 2 fdcad7 fdcad6 fdcad5 fdcad4 cr21 0111 1100 2 ide0ad7 ide0ad6 ide0ad5 ide0ad4 cr22 1111 1101 2 ide1ad7 ide1ad6 ide1ad5 ide1ad4 cr23 1101 1110 2 prtad7 prtad6 prtad5 prtad4 cr24 1111 1110 2 uraad7 uraad6 uraad5 uraad4 cr25 1011 1110 2 urbad7 urbad6 urbad5 urbad4 cr26 0010 0011 2 fdcdqs3 fdcdqs2 fdcdqs1 fdcdqs0 cr27 0000 0101 2 ecpirqx2 ecpirqx1 ecpirqx0 0 cr28 0100 0011 2 uraiqs3 uraiqs2 uraiqs1 uraiqs0 cr29 0110 0000 2 fdciqs3 fdciqs2 fdciqs1 fdciqs0 cr2a 0000 0000 irtxdsl3 irtxdsl2 irtxdsl1 irtxdsl0 cr2b 0000 0000 pin1fun1 pin1fun0 pin2fun1 pin2fun0 cr2c 0001 0000 pin91fn2 pin91fn1 pin91fn0 apedcrc notes: 1. ' s' means its value depends on corresponding power-on setting pin. 2. these default values are valid when cr16 bit 2 is 1 during power-on reset; they will be all 0's if cr16 bit 2 is 0.
138 table 8 - bit map of configuration registers (continued) register power-on reset value d3 d2 d1 d0 cr0 0000 0000 prtmods1 prtmods0 oscs1 oscs0 cr1 0000 0000 0 0 0 0 cr2 0000 0000 ra5 ra4 ra3 cea cr3 0011 0000 0 0 suamidi submidi cr4 0000 0000 prttri gmtri uratri urbtri cr5 0000 0000 ecpfthr3 ecpfthr2 ecpfthr1 ecpfthr0 cr6 0000 0000 fdcpwd idepwd fdctri idetri cr7 0000 0000 fdd b t1 fdd b t0 fdd a t1 fdd a t0 cr8 0000 0000 media 1 media 0 boot 1 boot 0 cr9 0000 1011 chip id 3 chip id 2 chip id 1 chip id 0 cra 0001 1111 pextadp pextepp pextecp pextecpp crb 0000 0000 ident mfm invertz drv2en crc 0010 1000 urirsel 0 rx2inv tx2inv crd 1010 0011 hduplx irmode2 irmode1 irmode0 cr10 0000 0000 gio0ad3 gio0ad2 gio0ad1 gio0ad0 cr11 0000 0000 0 gio0ad10 gio0ad9 gio0ad8 cr12 0000 0000 gio1ad3 gio1ad2 gio1ad1 gio1ad0 cr13 0000 0000 0 gio1ad10 gio1ad9 gio1ad8 cr14 0000 0000 gcs0ior gcs0iow gda0opi gda0ipi cr15 0000 0000 gcs1ior gcs1iow gda1opi gda1ipi cr16 000s ssss 1 gmdrq pnpcvs iride hefras cr17 0000 0000 dsfdlgrq dsprlgrq dsualgrq dsublgrq cr1e 1000 0001 2 gmad3 gmad2 gmas1 gmas0 cr20 1111 1100 2 fdcad3 fdcad2 0 0 cr21 0111 1100 2 ide0ad3 ide0ad2 0 0 cr22 1111 1101 2 ide1ad3 ide1ad2 0 1 cr23 1101 1110 2 prtad3 prtad2 prtad1 prtad0 cr24 1111 1110 2 uraad3 uraad2 uraad1 0 cr25 1011 1110 2 urbad3 urbad2 urbad1 0 cr26 0010 0011 2 prtdqs3 prtdqs2 prtdqs1 prtdqs0 cr27 0000 0101 2 prtiqs3 prtiqs2 prtiqs1 prtiqs0 cr28 0100 0011 2 urbiqs3 urbiqs2 urbiqs1 urbiqs0 cr29 0110 0000 2 iqniqs3 iqniqs2 iqniqs1 iqniqs0 cr2a 0000 0000 irrxdsl3 irrxdsl2 irrxdsl1 irrxdsl0 cr2b 0000 0000 pin3fun1 pin3fun0 pin93fn1 pin93fn0 cr2c 0001 0000 enbnksl clkinsl 0 0 notes: 1. ' s' means its value depends on corresponding power-on setting pin. 2. these default values are valid when cr16 bit 2 is 1 during power-on reset; they will be all 0's if cr16 bit 2 is 0.
139 specifications absolute maximum ratings parameter rating unit power supply voltage -0.5 to 7.0 v input voltage -0.5 to v dd +0.5 v operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (ta = 0 c to 70 c, vdd = 5v 10%, vss = 0v) parameter sym. min. max. unit conditions i/o 8t - ttl level bi-directional pin with source-sink capabilities of 8 ma input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v dd + 0.5 v output low voltage v ol 0.4 v i ol = 8 ma output high voltage v oh 2.4 v i oh = -8 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v i/o 12t - ttl level bi-directional pin with source-sink capabilities of 12 ma input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v dd + 0.5 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v i/o 24t - ttl level bi-directional pin with source-sink capabilities of 24 ma input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v dd + 0.5 v output low voltage v ol 0.4 v i ol = 24 ma output high voltage v oh 2.4 v i oh = -24 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v out 8t - ttl level output pin with source-sink capabilities of 8 ma output low voltage v ol 0.4 v i ol = 8 ma output high voltage v oh 2.4 v i oh = -8 ma out 12t - ttl level output pin with source-sink capabilities of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma od 12 - open-drain output pin with sink capabilities of 12 ma output low voltage v ol 0.4 v i ol = 12 ma od 24 - open-drain output pin with sink capabilities of 24 ma output low voltage v ol 0.4 v i ol = 24 ma in t - ttl level input pin
140 parameter sym. min. max. unit conditions input low voltage v il -0.5 0.8 v input high voltage v ih 2.0 v dd + 0.5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v in c - cmos level input pin input low voltage v il -0.5 0.3 v dd v input high voltage v ih 0.7 v dd v dd + 0.5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v in cs - cmos level schmitt-triggered input pin input low voltage v il -0.5 1.8 v input high voltage v ih 3.0 v dd + 0.5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil -10 m a v in = 0v
141 ac characteristics fdc: data rate = 1 mb/500 kb/300 kb/250 kb/sec. parameter sym. test conditions min. typ. (note 1) max. unit sa9-sa0, aen, ndack, ncs, setup time to nior tar 25 ns sa9-sa0, aen, ndack, hold time for nior tar 0 ns nior width trr 80 ns data access time from nior tfd cl = 100 pf 80 ns data hold from nior tdh cl = 100 pf 10 ns sd to from nior tdf cl = 100 pf 10 50 ns irq delay from nior tri 360/570 /675 ns sa9-sa0, aen, ndack, setup time to niow taw 25 ns sa9-sa0, aen, ndack, hold time for niow twa 0 ns niow width tww 60 ns data setup time to niow tdw 60 ns data hold time from niow twd 0 ns irq delay from niow twi 360/570 /675 ns drq cycle time tmcy 27 m s drq delay time ndack tam 50 ns drq to ndack delay tma 0 ns ndack width taa 260/ 430 /510 ns nior delay from ndrq tmr 0 ns niow delay from ndrq tmw 0 ns niow or nior response time from drq tmrw 6/12 /20/24 m s tc width ttc 135/ 220 /260 ns
142 parameter sym. test conditions min. typ. (note 1) max. unit reset width trst 1.8/3 /3.5 m s nindex width tidx 0.5/ 0.9 /1.0 m s ndir setup time to nstep tdst 1.0/ 1.6 /2.0 m s ndir hold time from nstep tstd 24/ 40/ 48 m s nstep pulse width tstp 6.8/ 11.5 /13.8 7/11.7 /14 7.2/11.9 /14.2 m s nstep cycle width tsc note 2 note 2 note 2 m s nwd pulse width twdd 100/ 185 /225 125/210 /250 150/235 /275 m s write precompensation twpc 100/ 138 /225 125/210 /250 150/235 /275 m s notes: 1. typical values for t = 25 c and normal supply voltage. 2. programmable from 2 ms through 32 ms in 2 ms increments. ide parameter symbol max. unit ncs0, ncs1 delay from sa valid t1 50 ns dbenl, dbenh delay from aen, iocs16, sa t2 50 ns ided7 to d7 delay (read cycle) t4 50 ns d7 to ided7 delay (write cycle) t3 50 ns
143 uart/parallel port parameter symbol test conditions min. max. unit delay from stop to set interrupt tsint 9/16 baud rate delay from nior reset interrupt trint 100 pf loading 1 m s delay from initial irq reset to transmit start tirs 1/16 8/16 baud rate delay from to reset interrupt thr 100 pf loading 175 ns delay from initial niow to interrupt tsi 9/16 16/16 baud rate delay from stop to set interrupt tsti 1/2 baud rate delay from nior to reset interrupt tir 100 pf loading 250 ns delay from niow to output tmwo 100 pf loading 200 ns set interrupt delay from modem input tsim 250 ns reset interrupt delay from nior trim 250 ns interrupt active delay tiad 100 pf loading 25 ns interrupt inactive delay tiid 100 pf loading 30 ns baud divisor n 100 pf loading 2 16 -1 extension adapter mode parameter sym. min. typ. max. unit nxrd, nxwr delay from nior, niow tx1 50 ns xa<0:2> delay from sa<0:2> tx2 50 ns xd<0:7> setup time tx3 50 ns xd<0:7> hold time tx4 0 ns irq & delay from xirq tx5 50 ns drqx delay from xdrq tx6 50 ns nxdack delay from ndackx tx7 50 ns xtc delay from tc tx8 50 ns
144 parallel port mode parameters parameter sym. min. max. unit pd0-7, nindex, nstrobe, nautofd delay from niow t1 100 ns irq delay from nack, nfault t2 60 ns irq delay from niow t3 105 ns irq active low in ecp and epp modes t4 200 300 ns nerror active to irq active t5 105 ns epp data or address read cycle timing parameters parameter sym. min. max. unit ax valid to nior asserted t1 40 ns iochrdy deasserted to nior deasserted t2 0 ns nior deasserted to ax valid t3 10 10 ns nior deasserted to niow or nior asserted t4 40 nior asserted to iochrdy asserted t5 0 24 ns pd valid to sd valid t6 0 75 ns nior deasserted to sd hi-z (hold time) t7 0 40 m s sd valid to iochrdy deasserted t8 0 85 ns nwait deasserted to iochrdy deasserted t9 60 160 ns pd hi-z to pdbir set t10 0 ns nwrite deasserted to nior asserted t13 0 ns nwait asserted to nwrite deasserted t14 0 185 ns nwait deasserted to nwrite modified t15 60 190 ns nior asserted to pd hi-z t16 0 50 ns nwait asserted to pd hi-z t17 60 180 ns command asserted to pd valid t18 0 ns command deasserted to pd hi-z t19 0 ns nwait deasserted to pd drive t20 60 190 ns nwrite deasserted to command t21 1 ns pbdir set to command t22 0 20 ns pd hi-z to command asserted t23 0 30 ns n wait asserted to command asserted t24 0 195 ns nwait deasserted to command deasserted t25 60 180 ns time out t26 10 12 ns pd valid to nwait deasserted t27 0 ns pd hi-z to nwait deasserted t28 0 m s
145 epp data or address write cycle timing parameters parameter sym. min. max. unit ax valid to niow asserted t1 40 ns sd valid to iow asserted t2 10 ns niow deasserted to ax invalid t3 10 ns nwait deasserted to iochrdy deasserted t4 0 ns command asserted to nwait deasserted t5 10 ns niow deasserted to niow or nior asserted t6 40 ns iochrdy deasserted to niow deasserted t7 0 24 ns nwait asserted to command asserted t8 60 160 ns niow asserted to nwait asserted t9 0 70 ns pbdir low to nwrite asserted t10 0 ns nwait asserted to nwrite asserted t11 60 185 ns nwait asserted to nwrite change t12 60 185 ns niow asserted to pd valid t13 0 50 ns nwait asserted to pd invalid t14 0 ns pd invalid to command asserted t15 10 ns niow to command asserted t16 5 35 ns nwait asserted to command asserted t17 60 210 ns nwait deasserted to command deasserted t18 60 190 ns command asserted to nwait deasserted t19 0 10 m s time out t20 10 12 m s command deasserted to nwait asserted t21 0 ns niow deasserted to nwrite deasserted and pd invalid t22 0 ns parallel port fifo timing parameters parameter symbol min. max. unit data valid to nstrobe active t1 600 ns nstrobe active pulse width t2 600 ns data hold from nstrobe inactive t3 450 ns busy inactive to pd inactive t4 80 ns busy inactive to nstrobe active t5 680 ns nstrobe active to busy active t6 500 ns
146 ecp parallel port forward timing parameters parameter symbol min. max. unit nautofd valid to nstrobe asserted t1 0 60 ns pd valid to nstrobe asserted t2 0 60 ns busy deasserted to nautofd changed t3 80 180 ns busy deasserted to pd changed t4 80 180 ns nstrobe deasserted to busy deasserted t5 0 ns busy deasserted to nstrobe asserted t6 80 200 ns nstrobe asserted to busy asserted t7 0 ns busy asserted to nstrobe deasserted t8 80 180 ns ecp parallel port reverse timing parameters parameter symbol min. max. unit pd valid to nack asserted t1 0 ns nautofd deasserted to pd changed t2 0 ns nautofd asserted to nack asserted t3 0 ns nautofd deasserted to nack deasserted t4 0 ns nack deasserted to nautofd asserted t5 80 200 ns pd changed to nautofd deasserted t6 80 200 ns
147 timing waveforms fdc processor read operation nwd write date aen sa0-sa9 ncs twdd tar tdh tdf tra index tidx tidx nindex taw twd twa processor write operation terminal count reset ttc tc trst reset dma operation irq d0 - d7 ndack nior irq d0-d7 aen sa0-sa9 ndack niow drive seek operation step ndir tdst tstp tstd trr tr tfd tsc tmw (niow) tmr (nior) tma tam drq ndack niow or nior tmcy taa tmrw tww twi tdw
148 t2 t1 t3 t4 niocs16 sa<0:9> data read ided7 d7 data write ided7 d7 nior niow ndbenh ndbenl ncs1 ncs0
149 uart/parallel trint star data bits (5-8) parity stop tsint star parity data (5-8) stop (1-2) star tir thr tsi thr thrs tsti sin (receiver input data) irq3 or irq4 ior (read receiver buffer register) serial out (sout) iow (write thr) irq3 or irq4 ior (read tir) receiver timing transmitter timing
150 modem control timing nack irq7 nri nior (read msr) niow (write mcr) nrts,ndtr ncts,ndsr ndcd modem control timing x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x tlid tlad printer interrupt timing tsim tmwo tmwo tsim trim trim tsim irq3 or irq4
151 parallel port parallel port timing niow ninit, nstrobe autofd, nslctin nack irq (spp) irq (epp or ecp) nfault (ecp) nerror (ecp) irq t1 t2 t3 t4 t5 t2 t4 pd<0:7>
152 epp data or address read cycle (epp version 1.9) nwrite datastb t13 t16 t14 t17 t22 t18 t23 t24 t21 t25 t19 t15 t20 addrstb nwait t26 t27 t28 pd<0:7> t1 iochrdy t3 t2 t4 t10 ior t5 t6 t7 t8 t9 sd<0:7> a<0:10>
153 epp data or address write cycle (epp version 1.9) t3 naddrstb a10-a0 niow iochrdy nwrite ndatast t1 t2 nwait t4 t5 t6 t20 t19 t7 t9 t10 t11 t13 t15 t16 t17 t22 t8 t18 t21 t12 t14 sd<0:7> pd<0:7> pbdir
154 epp data or address read cycle (epp version 1.7) nwrite datastb t13 t16 t14 t17 t22 t18 t23 t24 t21 t25 t19 t15 t20 addrstb nwait t26 t27 t28 pd<0:7> t1 iochrdy t3 t2 t4 t10 ior t5 t6 t7 t8 t9 sd<0:7> a<0:10>
155 epp data or address write cycle (epp version 1.7) parallel port fifo timing t3 naddrstb a10-a0 iochrdy nwrite ndatast t1 t2 niow nwait t4 t5 t6 t20 t19 t7 t9 t10 t11 t13 t15 t16 t17 t8 t18 t22 t22 sd<0:7> pd<0:7> nstrobe busy > t3 >| >| >| t1 >| t2 t6 >| t5 t4 pd<0:7>
156 ecp parallel port forward timing ecp parallel port reverse timing t3 nautofd t1 t2 nstrobe busy t5 t7 t5 t6 t8 t4 pd<0:7> t1 t5 nack nautofd t3 t6 t4 t5 t2 pd<0:7>
157 extension adapter mode command cycle extension adapter mode interrupt cycle tx3 tx4 tx2 tx1 nior niow nxrd nxwr sa<0:2> xa<0:2> xd<0:7> tx5 xirq irq7
158 extension adapter mode dma cycle application circuits parallel port extension fdd tx8 tx7 tx6 xdrq drqx ndackx nxdack tc xtc 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 nwe2/slct nwd2/pe nmob2/busy ndsb2/ack pd7 pd6 pd5 ndch2/pd4 rdd2/pd3 nstep2/nslin nwp2/pd2 ndir2/ninit ntrk02/pd1 nhead2/nerr nidx2/pd0 nrwc2/nafd nstb jp 13a ext fdc ndch2 ntrk02 nrdd2 ndir2 nwp2 nmob2 nrwc2 ndsb2 nhead2 nstep2 nwd2 nwe2 nidx2 parallel port extension fdd mode connection diagram
159 parallel port extension fdd 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 nwe2/slct nwd2/pe nmob2/busy ndsb2/ack pd5 ndch2/pd4 nrdd2/pd3 nstep2/nslin nwp2/pd2 ndir2/ninit ntrk02/pd1 nhead2/nerr nidx2/pd0 nrwc2/nafd nstb jp 13a ext fdc ndch2 ntrk02 nrdd2 ndir2 nwp2 nmob2 nrwc2 ndsb2 nhead2 nstep2 nwd2 nwe2 nidx2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 ndsa2 nmoa2 parallel port extension 2fdd connection diagram ndsa2/pd7 nmoa2/pd6
160 parallel port extension 2fdd 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 nwe2/slct nwd2/pe nmob2/busy ndsb2/ack pd5 ndch2/pd4 nrdd2/pd3 nstep2/nslin nwp2/pd2 ndir2/ninit ntrk02/pd1 nhead2/nerr nidx2/pd0 nrwc2/nafd nstb jp 13a ext fdc ndch2 ntrk02 nrdd2 ndir2 nwp2 nmob2 nrwc2 ndsb2 nhead2 nstep2 nwd2 nwe2 nidx2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 ndsa2 nmoa2 parallel port extension 2fdd connection diagram ndsa2/pd7 nmoa2/pd6
161 parallel port joystick mode four fdd mode signal joystick 15-pin connector printer port 25-pin connector vdd gnd d0 d1 d2 d3 d4 d5 d6 d7 1,8,9,15 4,5,12 3 6 nc nc 2 7 nc nc 1,14,15,16,17 18~25 2 3 4 5 6 7 8 9 printer port 25-pin connector 13 12 11 10 9 8 7 6 5 4 3 2 1 25 24 23 22 21 20 19 18 17 16 15 14 8 7 6 5 4 3 2 1 15 14 13 12 11 10 9 joystick 15-pin connector parallel port joystick mode connection diagram 81k 81k g1 a1 b1 g2 a2 b2 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 ndsa nmoa ndsa ndsb nmoa nmob fdc87w22 74ls139 7407(2) nmod nmoc nmob ndsc ndsd ndsb
162 package dimensions FDC87W21 (100 pin qfp) 51 50 31 30 1 80 81 100 h d d e b e h e 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.10 0 12 0 0.004 3.30 0.10 0.130 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm 12 2.40 1.40 19.10 1.20 18.80 1.00 18.49 0.094 0.055 0.988 0.752 0.047 0.976 0.740 0.039 0.964 0.728 0.65 20.13 14.13 0.25 0.40 2.97 20.00 14.00 2.85 19.87 13.87 0.10 0.25 2.73 0.792 0.556 0.010 0.016 0.117 0.787 0.551 0.112 0.026 0.782 0.546 0.004 0.010 0.107 0.012 0.006 0.15 0.30 24.49 24.80 25.10 0.020 0.087 0.032 0.103 0.50 0.80 2.21 2.62 a b c d e h d h e l y a a l 1 1 2 e q q 2 1 a y a a seating plane l l 1 see detail f detail f c q q
163
? 1998 standard microsystems corporation (smsc) circuit diagrams utilizing smsc products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. the information has been carefully checked and is believed to be entirely reliable. however, no responsibility is assumed for inaccuracies. furthermore, such information does not convey to the purchaser of the semiconduc tor devices described any licenses under the patent rights of smsc or others. smsc reserves the right to make changes at any time in order to improve design and supply the best product possible. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. FDC87W21 rev. 10/6/98

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